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Fully parallel implementation of timing-error-tolerant LDPC decoders

Fully parallel implementation of timing-error-tolerant LDPC decoders
Fully parallel implementation of timing-error-tolerant LDPC decoders
In this thesis, the design of fully parallel timing-error-tolerant Low-Density Parity-Check (LDPC) decoders have been investigated. LDPC decoders are employed in numerous communication systems to correct channel-induced transmission errors. The ever increasing data traffic demands require LDPC decoders that are capable of providing high processing throughput and low processing latency, using limited hardware resources and energy consumption. The fully parallel implementation of LDPC decoders is suitable, due to the high throughput and low latency that this affords. However, the task of designing reliable Very Large-Scale Integration (VLSI) systems is becoming increasingly challenging in successive generations of nanoscale fabrication technology. This may be attributed to the occurrence of timing errors, during the processing, which is caused by the increasing susceptibility to IR drop, inductive noise, crosstalk, electrostatic discharges, particle strikes, switching noise and fabrication process variations. Therefore it is necessary to consider the effects of timing errors during the design of LDPC decoders. However, the characterization of the timing error tolerance of LDPC decoders relying on measurements obtained directly from a fabricated Application-Specific Integrated Circuit (ASIC) may not be preferable, owing to the associated risk of wasting all of the invested time, effort and expense, if the ASIC is not able to facilitate the desired outcomes. A novel design flow is therefore proposed in this thesis, which allows the use of simulations at the algorithm level to investigate the decoders' error correction performance, with considerations of the occurrence of timing errors in the hardware architecture level of the design.

LDPC decoders employing the optimal Sum-Product Algorithm (SPA) have a very high implementation complexity, which requires the exchange of floating point probabilities between the parity-Check Nodes (CNs) and Variable Nodes (VNs) in their factor graph representation. In order to reduce the complexity, the Log-Sum-Product Algorithm(Log-SPA) and the Min-Sum Algorithm (MSA) may be employed in the LDPC decoder, which operate on a basis of Log-Likelihood Ratios (LLRs), rather than probabilities. These LLRs can be represented by Fixed-Point (FP) numbers, comprising a number of bits, referred to as the bit width. It is this bit width that proportionally determines both the size of the memory required, as well as the area of the data path and hence the energy consumption imposed. We propose the use of EXtrinsic Information Transfer (EXIT) charts to select the bit widths for the Fixed-point LDPC Decoders (LDPC-FDs), in order to achieve a desirable trade-off between the implementation complexity and the error correction performance. This significantly expedites the LDPC-FD design process, relative to the conventional approach of using trial and error based Bit Error Ratio (BER) simulations. Using the proposed design flow, timing characteristics analysis may be performed on the LDPC-FD, in order to derive an error model of the causes and effects of timing errors. With the aid of the error model, the error correction performance of the LDPC-FD in the presence of timing errors may be characterized. In this way, the parametrization of the LDPC-FD may be optimized.

In Stochastic LDPC Decoders (LDPC-SDs), only a single bit is exchanged between each pair of CNs and VNs in each clock cycle. Over the course of several successive clock cycles, the individual bits that are exchanged between a particular pair of nodes collectively form a Bernoulli sequence, which may replace the LLRs conventionally used in LDPC-FDs. Owing to this, the operations of the CNs and VNs may be implemented using simple logic gates, which grants LDPC-SDs the practical opportunity for fully parallel implementation. As in LDPC-FDs, the proposed design flow may be adopted to guide the investigation of the timing error tolerance of LDPC-SDs, in order to determine their optimal parametrization.
Zuo, Xin
99d84404-0d62-496b-945e-311feadcfc77
Zuo, Xin
99d84404-0d62-496b-945e-311feadcfc77
Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1

(2016) Fully parallel implementation of timing-error-tolerant LDPC decoders. University of Southampton, Faculty of Physical Sciences and Engineering, Doctoral Thesis, 176pp.

Record type: Thesis (Doctoral)

Abstract

In this thesis, the design of fully parallel timing-error-tolerant Low-Density Parity-Check (LDPC) decoders have been investigated. LDPC decoders are employed in numerous communication systems to correct channel-induced transmission errors. The ever increasing data traffic demands require LDPC decoders that are capable of providing high processing throughput and low processing latency, using limited hardware resources and energy consumption. The fully parallel implementation of LDPC decoders is suitable, due to the high throughput and low latency that this affords. However, the task of designing reliable Very Large-Scale Integration (VLSI) systems is becoming increasingly challenging in successive generations of nanoscale fabrication technology. This may be attributed to the occurrence of timing errors, during the processing, which is caused by the increasing susceptibility to IR drop, inductive noise, crosstalk, electrostatic discharges, particle strikes, switching noise and fabrication process variations. Therefore it is necessary to consider the effects of timing errors during the design of LDPC decoders. However, the characterization of the timing error tolerance of LDPC decoders relying on measurements obtained directly from a fabricated Application-Specific Integrated Circuit (ASIC) may not be preferable, owing to the associated risk of wasting all of the invested time, effort and expense, if the ASIC is not able to facilitate the desired outcomes. A novel design flow is therefore proposed in this thesis, which allows the use of simulations at the algorithm level to investigate the decoders' error correction performance, with considerations of the occurrence of timing errors in the hardware architecture level of the design.

LDPC decoders employing the optimal Sum-Product Algorithm (SPA) have a very high implementation complexity, which requires the exchange of floating point probabilities between the parity-Check Nodes (CNs) and Variable Nodes (VNs) in their factor graph representation. In order to reduce the complexity, the Log-Sum-Product Algorithm(Log-SPA) and the Min-Sum Algorithm (MSA) may be employed in the LDPC decoder, which operate on a basis of Log-Likelihood Ratios (LLRs), rather than probabilities. These LLRs can be represented by Fixed-Point (FP) numbers, comprising a number of bits, referred to as the bit width. It is this bit width that proportionally determines both the size of the memory required, as well as the area of the data path and hence the energy consumption imposed. We propose the use of EXtrinsic Information Transfer (EXIT) charts to select the bit widths for the Fixed-point LDPC Decoders (LDPC-FDs), in order to achieve a desirable trade-off between the implementation complexity and the error correction performance. This significantly expedites the LDPC-FD design process, relative to the conventional approach of using trial and error based Bit Error Ratio (BER) simulations. Using the proposed design flow, timing characteristics analysis may be performed on the LDPC-FD, in order to derive an error model of the causes and effects of timing errors. With the aid of the error model, the error correction performance of the LDPC-FD in the presence of timing errors may be characterized. In this way, the parametrization of the LDPC-FD may be optimized.

In Stochastic LDPC Decoders (LDPC-SDs), only a single bit is exchanged between each pair of CNs and VNs in each clock cycle. Over the course of several successive clock cycles, the individual bits that are exchanged between a particular pair of nodes collectively form a Bernoulli sequence, which may replace the LLRs conventionally used in LDPC-FDs. Owing to this, the operations of the CNs and VNs may be implemented using simple logic gates, which grants LDPC-SDs the practical opportunity for fully parallel implementation. As in LDPC-FDs, the proposed design flow may be adopted to guide the investigation of the timing error tolerance of LDPC-SDs, in order to determine their optimal parametrization.

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Published date: January 2016
Organisations: University of Southampton, EEE

Identifiers

Local EPrints ID: 400192
URI: http://eprints.soton.ac.uk/id/eprint/400192
PURE UUID: c3fda0fd-861d-47ed-b07c-520c85f2d588
ORCID for Lajos Hanzo: ORCID iD orcid.org/0000-0002-2636-5214

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Date deposited: 22 Sep 2016 13:03
Last modified: 30 Jun 2019 04:01

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