A flexible FPGA-based quasi-cyclic LDPC decoder
A flexible FPGA-based quasi-cyclic LDPC decoder
Low-Density Parity Check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of LDPC decoder designs on Field-Programmable Gate Array (FPGA) devices, in order to exploit their high processing speed, parallelism and re-programmability. Meanwhile, a variety of Application-Specific Integrated Circuit (ASIC) implementations of multi-mode LDPC decoders exhibiting both inter-standard and intra-standard reconfiguration flexibility are available in the open literature. However, the high complexity of the adaptable routing and processing elements that are required by a flexible LDPC decoder has resulted in a lack of viable FPGA-based implementations. Hence in this work, we propose a parameterisable FPGA-based LDPC decoder architecture, which supports run-time flexibility over any set of one or more Quasi-Cyclic (QC) LDPC codes. Additionally, we propose an offline design flow, which may be used to automatically generate an optimised HDL description of our decoder, having support for a chosen selection of codes. Our implementation results show that the proposed architecture achieves a high level of design-time and run-time flexibility, whilst maintaining a reasonable processing throughput, hardware resource requirement and error correction performance.
20965-20984
Hailes, Peter
952615b5-67fc-4978-a886-c407ae62b892
Xu, Lei
e55a381b-bd10-4303-9653-da27302d7303
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1
25 October 2017
Hailes, Peter
952615b5-67fc-4978-a886-c407ae62b892
Xu, Lei
e55a381b-bd10-4303-9653-da27302d7303
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1
Hailes, Peter, Xu, Lei, Maunder, Robert, Al-Hashimi, Bashir and Hanzo, Lajos
(2017)
A flexible FPGA-based quasi-cyclic LDPC decoder.
IEEE Access, 5, .
(doi:10.1109/ACCESS.2017.2678103).
Abstract
Low-Density Parity Check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of LDPC decoder designs on Field-Programmable Gate Array (FPGA) devices, in order to exploit their high processing speed, parallelism and re-programmability. Meanwhile, a variety of Application-Specific Integrated Circuit (ASIC) implementations of multi-mode LDPC decoders exhibiting both inter-standard and intra-standard reconfiguration flexibility are available in the open literature. However, the high complexity of the adaptable routing and processing elements that are required by a flexible LDPC decoder has resulted in a lack of viable FPGA-based implementations. Hence in this work, we propose a parameterisable FPGA-based LDPC decoder architecture, which supports run-time flexibility over any set of one or more Quasi-Cyclic (QC) LDPC codes. Additionally, we propose an offline design flow, which may be used to automatically generate an optimised HDL description of our decoder, having support for a chosen selection of codes. Our implementation results show that the proposed architecture achieves a high level of design-time and run-time flexibility, whilst maintaining a reasonable processing throughput, hardware resource requirement and error correction performance.
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Accepted/In Press date: 1 March 2017
e-pub ahead of print date: 3 March 2017
Published date: 25 October 2017
Organisations:
Electronics & Computer Science, Faculty of Physical Sciences and Engineering, Southampton Wireless Group
Identifiers
Local EPrints ID: 406883
URI: http://eprints.soton.ac.uk/id/eprint/406883
PURE UUID: d68e345f-bf40-4ef8-91d1-0daf915d3164
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Date deposited: 25 Mar 2017 02:04
Last modified: 18 Mar 2024 03:09
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Author:
Peter Hailes
Author:
Lei Xu
Author:
Robert Maunder
Author:
Bashir Al-Hashimi
Author:
Lajos Hanzo
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