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Leakage current analysis for diagnosis of bridge defects in power-gating designs

Leakage current analysis for diagnosis of bridge defects in power-gating designs
Leakage current analysis for diagnosis of bridge defects in power-gating designs
Manufacturing defects that do not affect the functional operation of low power Integrated Circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS'05 benchmarks synthesised using a 32 nm CMOS technology, the trade-offs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of R>10MOhm (weak bridges) and bridges of R<10MOhm (strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27K and 157K gate equivalents, respectively.
Bridge circuits, Power supplies , Logic gates, Leakage currents, System-on-chip, Rails, Circuit faults
0278-0070
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Chakrabarty, Krishnendu
a8afcb71-145f-4def-ac52-e03ecc47863f
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Chakrabarty, Krishnendu
a8afcb71-145f-4def-ac52-e03ecc47863f

Tenentes, Vasileios, Rossi, Daniele, Khursheed, Saqib, Al-Hashimi, Bashir and Chakrabarty, Krishnendu (2017) Leakage current analysis for diagnosis of bridge defects in power-gating designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (doi:10.1109/TCAD.2017.2729462).

Record type: Article

Abstract

Manufacturing defects that do not affect the functional operation of low power Integrated Circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS'05 benchmarks synthesised using a 32 nm CMOS technology, the trade-offs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of R>10MOhm (weak bridges) and bridges of R<10MOhm (strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27K and 157K gate equivalents, respectively.

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TCAD-Accepted - Accepted Manuscript
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Accepted/In Press date: 9 June 2017
e-pub ahead of print date: 19 July 2017
Keywords: Bridge circuits, Power supplies , Logic gates, Leakage currents, System-on-chip, Rails, Circuit faults

Identifiers

Local EPrints ID: 412771
URI: https://eprints.soton.ac.uk/id/eprint/412771
ISSN: 0278-0070
PURE UUID: e25ef489-bd67-4cdf-a1fd-b53c5558a045

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Date deposited: 01 Aug 2017 16:31
Last modified: 02 Dec 2019 18:57

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Contributors

Author: Vasileios Tenentes
Author: Daniele Rossi
Author: Saqib Khursheed
Author: Bashir Al-Hashimi
Author: Krishnendu Chakrabarty

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