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A cost-efficient delay-fault monitor

Sai, Gaole, Halak, Basel and Zwolinski, Mark (2017) A cost-efficient delay-fault monitor In IEEE International Symposium on Circuits and Systems: ISCAS 2017. IEEE. 4 pp.

Record type: Conference or Workshop Item (Paper)


Delay-fault monitoring sensors are widely used for Dynamic Voltage and Frequency Scaling (DVFS) to compensate for intrinsic Process, Voltage, Temperature and Ageing (PVTA) variations. Such techniques are generally based on monitoring the circuit’s critical paths. This paper presents a new delay-fault monitoring circuit, which is able to monitoring multiple paths simultaneously. The proposed circuitry has been designed and verified in a 32 bit MIPS processor using a 65nm technology. Our results indicate that the use of the proposed sensor for delay monitoring can lead to a significant saving in area and power overheads of two-thirds and one-third, respectively, compared to a canary flip-flop.

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Published date: 28 May 2017


Local EPrints ID: 412775
PURE UUID: 9e9a863d-7e4e-4a9a-bee4-dde8f92f20cb
ORCID for Mark Zwolinski: ORCID iD

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Date deposited: 01 Aug 2017 16:31
Last modified: 01 Aug 2017 16:31

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Author: Gaole Sai
Author: Basel Halak
Author: Mark Zwolinski ORCID iD

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