Stress analysis and optimization of a Flip chip on flex electronic packaging method for functional electronic textiles
Stress analysis and optimization of a Flip chip on flex electronic packaging method for functional electronic textiles
A method for packaging integrated circuit (IC) silicon die in thin flexible circuits has been investigated that enables circuits to be subsequently integrated within textile yarns. This paper presents an investigation into the required materials and component dimensions in order to maximize the reliability of the packaging method. Two die sizes of 3.5 mm x 8 mm x 0.53 mm and 2 mm x 2mm x 0.1 mm have been simulated and evaluated experimentally under shear load and during bending. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. Three under-fill adhesives (EP30AO, EP37-3FLF and Epo-Tek 301 2fl), three highly flexible adhesive (Loctite 4860, Loctite 480 and Loctite 4902) and three substrates (Kapton, Mylar and PEEK) have been evaluated and the optimal thickness of each is found. The Kapton substrate, together with the EP37-3FLF adhesive, were identified as the best materials combination, with the optimum under-fill and substrate thickness identified as 0.05 mm.
186-194
Li, Menglong
23dd02ab-027d-46ca-a8eb-ac9b73f3916f
Tudor, John
46eea408-2246-4aa0-8b44-86169ed601ff
Torah, Russel
7147b47b-db01-4124-95dc-90d6a9842688
Beeby, Stephen
ba565001-2812-4300-89f1-fe5a437ecb0d
February 2018
Li, Menglong
23dd02ab-027d-46ca-a8eb-ac9b73f3916f
Tudor, John
46eea408-2246-4aa0-8b44-86169ed601ff
Torah, Russel
7147b47b-db01-4124-95dc-90d6a9842688
Beeby, Stephen
ba565001-2812-4300-89f1-fe5a437ecb0d
Li, Menglong, Tudor, John, Torah, Russel and Beeby, Stephen
(2018)
Stress analysis and optimization of a Flip chip on flex electronic packaging method for functional electronic textiles.
IEEE Transactions on Components Packaging and Manufacturing Technology, 8 (2), .
(doi:10.1109/TCPMT.2017.2780626).
Abstract
A method for packaging integrated circuit (IC) silicon die in thin flexible circuits has been investigated that enables circuits to be subsequently integrated within textile yarns. This paper presents an investigation into the required materials and component dimensions in order to maximize the reliability of the packaging method. Two die sizes of 3.5 mm x 8 mm x 0.53 mm and 2 mm x 2mm x 0.1 mm have been simulated and evaluated experimentally under shear load and during bending. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. Three under-fill adhesives (EP30AO, EP37-3FLF and Epo-Tek 301 2fl), three highly flexible adhesive (Loctite 4860, Loctite 480 and Loctite 4902) and three substrates (Kapton, Mylar and PEEK) have been evaluated and the optimal thickness of each is found. The Kapton substrate, together with the EP37-3FLF adhesive, were identified as the best materials combination, with the optimum under-fill and substrate thickness identified as 0.05 mm.
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Stress Analysis and Optimization of a Flip Chip on Flex Electronic Packaging Method for Functional Electronic Textiles
- Accepted Manuscript
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Accepted/In Press date: 3 December 2017
e-pub ahead of print date: 27 December 2017
Published date: February 2018
Identifiers
Local EPrints ID: 416842
URI: http://eprints.soton.ac.uk/id/eprint/416842
ISSN: 2156-3950
PURE UUID: 36db461c-839b-4698-b177-da7770736efd
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Date deposited: 11 Jan 2018 17:30
Last modified: 16 Mar 2024 03:40
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