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Passively aligned packaging solutions for silicon photonics

Passively aligned packaging solutions for silicon photonics
Passively aligned packaging solutions for silicon photonics
Packaging is a critical component in bringing silicon photonics to application. Without low cost, high throughput packaging, the per‐unit cost of silicon photonic integrated circuits will be too high for mass markets.

Passive alignment of optical fibres to silicon photonic waveguides would significantly reduce the assembly time currently required where active alignment is labour intensive and time consuming.

In this work a design is presented that has the potential for high volume cost effective packaging. The design accomplishes this by supporting and positioning multiple fibres relative to a silicon photonic integrated circuit. The capping chip passively aligns the fibres to silicon nanowires via a grating couplers. V‐groove structures in the capping chip are used to support and position the fibres and the end facet of the v‐groove reflects the light down on to the grating coupler. Plugs on the capping chip align with holes on the photonic chip assuring accurate positioning and optimal coupling.

The processing required has been detailed and demonstrated, including a hybrid lithography process, crystallographically aligned v‐grooves and highly accurate alignment structures. Once combined these processes will passively align fibre optic cables with silicon photonic waveguide gratings with a misalignment less than 2μm which in theory will produce an added loss less than 1dB, grating couplers have been produced based on a bespoke design fitting the demands of the packaging solution and show a loss of 2.7dB with room for improvement compared to a simulated result of 1.67dB.
University of Southampton
Reynolds, Scott
ed8f5413-c0c0-4449-ba35-626485f23a75
Reynolds, Scott
ed8f5413-c0c0-4449-ba35-626485f23a75
Reed, Graham
ca08dd60-c072-4d7d-b254-75714d570139

Reynolds, Scott (2016) Passively aligned packaging solutions for silicon photonics. University of Southampton, Doctoral Thesis, 141pp.

Record type: Thesis (Doctoral)

Abstract

Packaging is a critical component in bringing silicon photonics to application. Without low cost, high throughput packaging, the per‐unit cost of silicon photonic integrated circuits will be too high for mass markets.

Passive alignment of optical fibres to silicon photonic waveguides would significantly reduce the assembly time currently required where active alignment is labour intensive and time consuming.

In this work a design is presented that has the potential for high volume cost effective packaging. The design accomplishes this by supporting and positioning multiple fibres relative to a silicon photonic integrated circuit. The capping chip passively aligns the fibres to silicon nanowires via a grating couplers. V‐groove structures in the capping chip are used to support and position the fibres and the end facet of the v‐groove reflects the light down on to the grating coupler. Plugs on the capping chip align with holes on the photonic chip assuring accurate positioning and optimal coupling.

The processing required has been detailed and demonstrated, including a hybrid lithography process, crystallographically aligned v‐grooves and highly accurate alignment structures. Once combined these processes will passively align fibre optic cables with silicon photonic waveguide gratings with a misalignment less than 2μm which in theory will produce an added loss less than 1dB, grating couplers have been produced based on a bespoke design fitting the demands of the packaging solution and show a loss of 2.7dB with room for improvement compared to a simulated result of 1.67dB.

Text
Final Thesis 13072016 Final Edit - Version of Record
Available under License University of Southampton Thesis Licence.
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Published date: 22 July 2016

Identifiers

Local EPrints ID: 419478
URI: http://eprints.soton.ac.uk/id/eprint/419478
PURE UUID: 2f37cc5a-7922-4f66-80d4-d3855f052070

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Date deposited: 12 Apr 2018 16:31
Last modified: 13 Mar 2019 18:46

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