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Low-power and low-cost dedicated bit-serial hardware neural network for epileptic seizure prediction system

Low-power and low-cost dedicated bit-serial hardware neural network for epileptic seizure prediction system
Low-power and low-cost dedicated bit-serial hardware neural network for epileptic seizure prediction system

This paper presents results of using a simple bit-serial architecture as a method of designing an extremely low-power and low-cost neural network processor for epilepsy seizure prediction. The proposed concept is based on a novel bit-serial data processing unit (DPU) which implements the functionality of a complete neuron and uses bit-serial arithmetic. Arrays of DPUs are controlled by simple finite state machines. We show that epilepsy detection through such dedicated neural hardware is feasible and may facilitate development of wearable, low-cost and low-energy personalized seizure prediction equipment. The proposed processor extracts epileptic seizure characteristics from electroencephalogram (EEG) waveforms. In order to facilitate the classification of EEG waveforms we develop a dedicated feature extraction hardware that provides inputs to the neural network. This approach has been tested using various network configurations and has been compared with related work. A complete system which can predict epileptic seizures with high accuracy has been implemented on an ALTERA Cyclone V FPGA using 3931 ALMs which constitutes about 7% of the Cyclone V A7 capacity. The design has a prediction accuracy of 90%.

Artificial Neural Networks (ANN), bit-serial neural processor, FPGA
1-9
Kueh, Si Mon
75e25e81-0593-4fc0-9374-93a9cc88235d
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a
Kueh, Si Mon
75e25e81-0593-4fc0-9374-93a9cc88235d
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a

Kueh, Si Mon and Kazmierski, Tom J. (2018) Low-power and low-cost dedicated bit-serial hardware neural network for epileptic seizure prediction system. IEEE Journal of Translational Engineering in Health and Medicine, 1-9. (doi:10.1109/JTEHM.2018.2867864).

Record type: Article

Abstract

This paper presents results of using a simple bit-serial architecture as a method of designing an extremely low-power and low-cost neural network processor for epilepsy seizure prediction. The proposed concept is based on a novel bit-serial data processing unit (DPU) which implements the functionality of a complete neuron and uses bit-serial arithmetic. Arrays of DPUs are controlled by simple finite state machines. We show that epilepsy detection through such dedicated neural hardware is feasible and may facilitate development of wearable, low-cost and low-energy personalized seizure prediction equipment. The proposed processor extracts epileptic seizure characteristics from electroencephalogram (EEG) waveforms. In order to facilitate the classification of EEG waveforms we develop a dedicated feature extraction hardware that provides inputs to the neural network. This approach has been tested using various network configurations and has been compared with related work. A complete system which can predict epileptic seizures with high accuracy has been implemented on an ALTERA Cyclone V FPGA using 3931 ALMs which constitutes about 7% of the Cyclone V A7 capacity. The design has a prediction accuracy of 90%.

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08456540 - Accepted Manuscript
Available under License Creative Commons Attribution.
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More information

Accepted/In Press date: 6 September 2018
e-pub ahead of print date: 6 September 2018
Keywords: Artificial Neural Networks (ANN), bit-serial neural processor, FPGA

Identifiers

Local EPrints ID: 423158
URI: https://eprints.soton.ac.uk/id/eprint/423158
PURE UUID: 8813d4df-45b3-4ab7-a1ff-3cc729a9811f

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Date deposited: 19 Sep 2018 16:30
Last modified: 19 Jul 2019 16:59

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