The University of Southampton
University of Southampton Institutional Repository

Clock generation for silicon photonics based optical communication systems

Clock generation for silicon photonics based optical communication systems
Clock generation for silicon photonics based optical communication systems
As communications data traffic continues to increase, electronic interconnects over short reaches are struggling to keep up with the bandwidth and power consumption requirements. One of the technology trends is to migrate from copper to optical based interconnects where silicon Photonics (SiP) technology has emerged as an excellent technical solution to meet the performance and cost requirements of these short-reach applications.

The clock generation system is a critical module that none of the communication systems can overlook. However, the reported clock generation solutions utilized in SiP transceivers inherit limitations from traditional electronic interconnects, where the clock signals are limited by the frequency tuning range, system settling time and the number of clock phases. The motivation for this PhD project is to build a novel clock generation system that can be fully integrated with future SiP transceiver and the innovation has been realized in various aspects of the work.

Firstly, a novel high-speed ring-based voltage-controlled oscillator (VCO) is proposed using inductor peaking. The proposed VCO topology was validated with four design examples fabricated in different CMOS processes nodes (130nm and 65nm) and measured results show close agreement with theoretical analysis. The figure of merit (FOM) of 203 is the best combination of frequency and tuning range currently.
Secondly, a dedicated phase locked loop (PLL) structure combined with the inductor peaking VCO was created, focussing on the requirements of frequency controllability and system settling time for SiP communication system. A programmable frequency range of more than 25GHz has been achieved using a 40nm process while the measured phase locking time is always less than half of a microsecond.

Finally, with the mainstream CMOS process for analogue circuits design migrating towards to 28nm High-k/Metal Gate (HKMG), design methodologies on the proposed VCO have been realized in order to adapt this evolution. Two specific design cases have been implemented to fully utilize the advantages of new CMOS process and mitigate the side-effects of 28nm HKMG process.
University of Southampton
Meng, Fanfan
3c45926e-5e27-4c33-8601-ccf624b240c2
Meng, Fanfan
3c45926e-5e27-4c33-8601-ccf624b240c2
Reed, Graham
ca08dd60-c072-4d7d-b254-75714d570139
Li, Ke
dd788ca7-0a39-4364-b4b8-65f0bb93340f
Thomson, David
17c1626c-2422-42c6-98e0-586ae220bcda
Lacava, Cosimo
a0a31a27-23ac-4a73-8bb4-2f02368fb8bd
Littlejohns, Callum
0fd6585d-030d-4d8f-a411-6fc03e083efa
Byers, James
124172c9-0709-4cb9-992e-acedc2eb02bf
Mailis, Sakellaris
233e0768-3f8d-430e-8fdf-92e6f4f6a0c4
Peacock, Anna
685d924c-ef6b-401b-a0bd-acf1f8e758fc
Husain, Muhammad K
92db1f76-6760-4cf2-8e30-5d4a602fe15b
Gardes, Frederic
7a49fc6d-dade-4099-b016-c60737cb5bb2
Saito, Shinichi
14a5d20b-055e-4f48-9dda-267e88bd3fdc

Meng, Fanfan (2018) Clock generation for silicon photonics based optical communication systems. University of Southampton, Doctoral Thesis, 227pp.

Record type: Thesis (Doctoral)

Abstract

As communications data traffic continues to increase, electronic interconnects over short reaches are struggling to keep up with the bandwidth and power consumption requirements. One of the technology trends is to migrate from copper to optical based interconnects where silicon Photonics (SiP) technology has emerged as an excellent technical solution to meet the performance and cost requirements of these short-reach applications.

The clock generation system is a critical module that none of the communication systems can overlook. However, the reported clock generation solutions utilized in SiP transceivers inherit limitations from traditional electronic interconnects, where the clock signals are limited by the frequency tuning range, system settling time and the number of clock phases. The motivation for this PhD project is to build a novel clock generation system that can be fully integrated with future SiP transceiver and the innovation has been realized in various aspects of the work.

Firstly, a novel high-speed ring-based voltage-controlled oscillator (VCO) is proposed using inductor peaking. The proposed VCO topology was validated with four design examples fabricated in different CMOS processes nodes (130nm and 65nm) and measured results show close agreement with theoretical analysis. The figure of merit (FOM) of 203 is the best combination of frequency and tuning range currently.
Secondly, a dedicated phase locked loop (PLL) structure combined with the inductor peaking VCO was created, focussing on the requirements of frequency controllability and system settling time for SiP communication system. A programmable frequency range of more than 25GHz has been achieved using a 40nm process while the measured phase locking time is always less than half of a microsecond.

Finally, with the mainstream CMOS process for analogue circuits design migrating towards to 28nm High-k/Metal Gate (HKMG), design methodologies on the proposed VCO have been realized in order to adapt this evolution. Two specific design cases have been implemented to fully utilize the advantages of new CMOS process and mitigate the side-effects of 28nm HKMG process.

Text
Final thesis - Version of Record
Available under License University of Southampton Thesis Licence.
Download (10MB)

More information

Published date: February 2018

Identifiers

Local EPrints ID: 423549
URI: http://eprints.soton.ac.uk/id/eprint/423549
PURE UUID: 970eb87a-87d8-49c8-ad9e-fe0299a89ac0
ORCID for Cosimo Lacava: ORCID iD orcid.org/0000-0002-9950-8642
ORCID for Sakellaris Mailis: ORCID iD orcid.org/0000-0001-8100-2670
ORCID for Anna Peacock: ORCID iD orcid.org/0000-0002-1940-7172
ORCID for Shinichi Saito: ORCID iD orcid.org/0000-0003-1539-1182

Catalogue record

Date deposited: 26 Sep 2018 16:30
Last modified: 14 Mar 2019 01:49

Export record

Download statistics

Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.

View more statistics

Atom RSS 1.0 RSS 2.0

Contact ePrints Soton: eprints@soton.ac.uk

ePrints Soton supports OAI 2.0 with a base URL of http://eprints.soton.ac.uk/cgi/oai2

This repository has been built using EPrints software, developed at the University of Southampton, but available to everyone to use.

We use cookies to ensure that we give you the best experience on our website. If you continue without changing your settings, we will assume that you are happy to receive cookies on the University of Southampton website.

×