Cai, Yunpeng and Savanth, Parameshwarappa Anand, Kumar (2018) Dataset for 'Ultra-Low Power 18-Transistor Fully-Static Contention-Free Single-Phase Clocked Flip-Flop in 65nm CMOS'. University of Southampton doi:10.5258/SOTON/D0678 [Dataset]
Record type:
Dataset
Abstract
This dataset supports the article entitled "Ultra-Low Power 18-Transistor Fully-Static Contention-Free Single-Phase Clocked Flip-Flop in 65nm CMOS" accepted for publication in IEEE Journal of Solid State Circuits, October 2018
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P4_007_B22_85C1p2V66MHz_2018125_153335_AS.log
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P4_007_B22_25C1p2V66MHz_2018125_122931_AS.log
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P4_007_B22_0C1p2V66MHz_2018125_141242_AS.log
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More information
Published date: 2018
Related URLs:
Organisations:
Electronics & Computer Science, Electronics & Computer Science, Cyber Physical Systems
Identifiers
Local EPrints ID: 425060
URI: http://eprints.soton.ac.uk/id/eprint/425060
PURE UUID: 71623ad2-dc7c-4c6c-92f7-325f42ab6549
Catalogue record
Date deposited: 09 Oct 2018 16:31
Last modified: 12 Nov 2023 09:19
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Contributors
Creator:
Yunpeng Cai
Creator:
Parameshwarappa Anand, Kumar Savanth
Contributor:
Pranay Prabhat
Contributor:
James Myers
Research team head:
Alexander Weddell
Research team head:
Tomasz Kazmierski
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