Design, Fabrication and Characterization of High Performance Zinc Oxide Nanowire Field-Effect Transistors

Abstract

This research project is focused on the optimization and electrical enhancement of zinc oxide (ZnO) nanowire field-effect transistors by remote plasma atomic layer deposition. Three device configurations have been fabricated based on a top-down fabrication method with channel lengths in the range of 18.6 μm to 1.3 μm. These devices were produced in well-defined locations on a 150 mm diameter silicon wafer. Controllable nanowire FET dimensions and locations are seen as fundamental to wafer-scale nanowire integrated circuit fabrication. Measured electrical results show n-type depletion behaviour with good electrical characteristics for all device configurations.

The first device configuration was fabricated with optimization of a top-down process based on a spacer method, aiming to reduce the sidewall roughness of the nanowire. The approach included the top-down nanowire process with reduced sidewall roughness during pattern transfer and the improvement of the electrical characteristics. The process involved a photoresist reflow technique and dry oxidation of the etched silicon sidewalls. The optimized top-down fabrication and sidewall resist smoothing were shown to produce ZnO nanowire FETs with good electrical characteristics for channel length devices of 1.3 μm, 8.6 μm, and 18.6 μm. The optimized device is able to produce a high output drain current by a factor of three, steep subthreshold slope of 800 mV/decade and a transconductance value of 5.9 nS, which is two times higher than the device from an un-optimized fabrication process.

In the second device configuration, the aim was to improve the contact resistance between the ZnO nanowire channel and source/drain contact as well as the mobility of the ZnO nanowire FET. Enhanced performance of the ZnO nanowire FET is demonstrated by depositing an Al-doped ZnO (AZO) thin film between the ZnO nanowires and the source/drain aluminium contact. This highly conductive AZO thin film is deposited via a thermal atomic layer deposition (ALD) at 200 oC and forms a bi-layer source/drain contact. The contact resistance was reduced from 194.1 Ω with aluminium contact to only 9.6 Ω using AZO. The field-effect mobility of ZnO nanowire FETs with AZO increases from 3.5 cm2/Vs to 85.7 cm2/Vs in dual nanowires. The AZO layer is seen as a promising source/drain contact material for the fabrication of high performance ZnO nanowire FETs. The ZnO nanowire FET with AZO thin film as the source/drain contact is further investigated by measuring the temperature-dependant electrical characteristics. The transfer curves shows a parallel shift toward negative voltage as the temperature increased from 200 K to 300 K.

In the third device configuration, the new fabrication method using direct photolithography and lateral wet etching was used to simplify the fabrication of top-down ZnO nanowire FETs and to avoid the disadvantage of the spacer method. This particular method is a preliminary attempt towards achieving high electrical performance in ZnO nanowire FETs for RF and logic circuit applications. This novel technique allows for the formation of nanowire FET with minimal impact from ions and chemical radicals during the anisotropic dry etching process. Except for the low field-effect mobility, this experiment demonstrated desirable electrical characteristics. Bottom-gate ZnO nanowire FETs with different gate lengths show a threshold voltage between -0.7 V to 1.5 V, on/off current ratio up to 107 and a subthreshold swing between 200 mV/decade to 300 mV/decade. This top-down fabrication method with low temperature film deposition encourages further research regarding the RF characterization of ZnO nanowire FETs and the adaptability of a RF device using ZnO nanowire FETs.

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Identifiers

ORCID for Harold Chong: orcid.org/0000-0002-7110-5761

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