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Design and implementation of flexible FPGA-based LDPC decoders

Design and implementation of flexible FPGA-based LDPC decoders
Design and implementation of flexible FPGA-based LDPC decoders
Since their rediscovery in the mid-1990s, Low-Density Parity Check (LDPC) error correction decoders have been the focus of a great deal of research within the communications community. They have also become popular channel coding schemes in a plethora of diverse communications standards, as a benefit of their strong error correction performance, low-complexity computations, and their suitability to parallel hardware implementation. Meanwhile, a great deal of research effort has been invested into LDPC decoder designs that exploit the high processing speed and parallelism of Field-Programmable Gate Array (FPGA) devices, which now constitute a cost-effective alternative to Application-Specific Integrated Circuit (ASIC) platforms for LDPC decoder implementations. However, the FPGA-based LDPC decoder designs published in the open literature vary greatly in terms of design choices and performance criteria, making them a challenge to compare and even more challenging to implement.

In this thesis, we explore the key factors involved in FPGA-based LDPC decoder design and present an extensive review of the current literature, analysing and characterising the performance tradeoffs demonstrated across over 140 competing designs. From this survey, we conclude that high-performance FPGA-based LDPC decoder designs supporting the ability to dynamically alter their decoding parameters at run-time are under-represented within the state-of-the-art, despite their necessity in order to comply with many modern communications standards.

Accordingly, this thesis therefore proposes two parameterised FPGA-based LDPC decoder architectures, which both support run-time flexibility over any arbitrary set of one or more Quasi-Cyclic (QC) LDPC codes. Our first architecture adopts a traditional fixed-point message decoding algorithm, but features a variety of design optimisations which reduce the costs of supporting multiple diverse codes. Implementation results of this decoder indicate that it is capable of achieving throughputs that are higher than previous flexible FPGA-based LDPC decoders, even whilst achieving the desired level of flexibility and satisfactorily high error correction performance.
University of Southampton
Hailes, Peter
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Hailes, Peter
deab6991-13c5-4e83-b185-fef11f174421
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, Bashir
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Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1
Xu, Lei
2bb029a5-26b2-495c-976a-7e13e38ec709

Hailes, Peter (2018) Design and implementation of flexible FPGA-based LDPC decoders. University of Southampton, Doctoral Thesis, 196pp.

Record type: Thesis (Doctoral)

Abstract

Since their rediscovery in the mid-1990s, Low-Density Parity Check (LDPC) error correction decoders have been the focus of a great deal of research within the communications community. They have also become popular channel coding schemes in a plethora of diverse communications standards, as a benefit of their strong error correction performance, low-complexity computations, and their suitability to parallel hardware implementation. Meanwhile, a great deal of research effort has been invested into LDPC decoder designs that exploit the high processing speed and parallelism of Field-Programmable Gate Array (FPGA) devices, which now constitute a cost-effective alternative to Application-Specific Integrated Circuit (ASIC) platforms for LDPC decoder implementations. However, the FPGA-based LDPC decoder designs published in the open literature vary greatly in terms of design choices and performance criteria, making them a challenge to compare and even more challenging to implement.

In this thesis, we explore the key factors involved in FPGA-based LDPC decoder design and present an extensive review of the current literature, analysing and characterising the performance tradeoffs demonstrated across over 140 competing designs. From this survey, we conclude that high-performance FPGA-based LDPC decoder designs supporting the ability to dynamically alter their decoding parameters at run-time are under-represented within the state-of-the-art, despite their necessity in order to comply with many modern communications standards.

Accordingly, this thesis therefore proposes two parameterised FPGA-based LDPC decoder architectures, which both support run-time flexibility over any arbitrary set of one or more Quasi-Cyclic (QC) LDPC codes. Our first architecture adopts a traditional fixed-point message decoding algorithm, but features a variety of design optimisations which reduce the costs of supporting multiple diverse codes. Implementation results of this decoder indicate that it is capable of achieving throughputs that are higher than previous flexible FPGA-based LDPC decoders, even whilst achieving the desired level of flexibility and satisfactorily high error correction performance.

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Published date: June 2018

Identifiers

Local EPrints ID: 429743
URI: http://eprints.soton.ac.uk/id/eprint/429743
PURE UUID: 487f07e7-1f45-4829-9fa2-de2d2b3f7f69
ORCID for Peter Hailes: ORCID iD orcid.org/0000-0002-0995-7947
ORCID for Robert Maunder: ORCID iD orcid.org/0000-0002-7944-2615
ORCID for Lajos Hanzo: ORCID iD orcid.org/0000-0002-2636-5214

Catalogue record

Date deposited: 04 Apr 2019 16:30
Last modified: 05 Apr 2019 00:38

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Contributors

Author: Peter Hailes ORCID iD
Thesis advisor: Robert Maunder ORCID iD
Thesis advisor: Bashir Al-Hashimi
Thesis advisor: Lajos Hanzo ORCID iD
Thesis advisor: Lei Xu

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