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Hardware-validated performance and power modelling of heterogeneous multi-processing architectures

Hardware-validated performance and power modelling of heterogeneous multi-processing architectures
Hardware-validated performance and power modelling of heterogeneous multi-processing architectures
Modern processors are becoming increasingly more complex and utilise higher numbers of Heterogeneous Multi-Processing (HMP) cores. Energy-efficiency has become the primary design constraint in recent years, and improvements enable battery-powered devices to run longer and reduce the energy and cooling costs in data centres. Moreover, increased energy-efficiency enables greater peak performance under the thermal and power constraints, enabling innovative new uses and applications. Accurate run-time power estimations are critical in guiding online energy-saving techniques and energy-aware scheduling decisions to find the optimum performance, power and energy tradeoff. This thesis presents a statistically-rigorous methodology for developing accurate and stable empirical power models for providing run-time power estimations to a run-time manager (RTM) while considering thermal variation, coefficient stability, heteroscedasticity, robust model specification, and non-ideal voltage regulation. The novel methodology ensures that the models perform significantly more accurately across a wider range of workloads when compared with existing runtime power modelling methodologies, achieving average errors lower than four percent. Practical considerations and shortcomings in existing approaches are also identified and addressed.

Furthermore, the recent slowdown in technology scaling has forced researchers and engineers to rely on micro-architectural advances and system-level optimisations to drive performance improvement, the development of which is underpinned by simulation tools. However, such simulation tools inevitably have limitations and contain sources of error which, if not understood by the user, can lead to inaccurate results and incorrect conclusions. This thesis presents a methodology for evaluating CPU performance models and identifying specific sources of error, allowing such models to be improved; extended to other CPUs; validated after changes; and tested for suitability to a specific use case. These hardware-validated performance models are combined with the empirical power models to enable accurate and reliable performance, power and energy simulation.

Moreover, the Powmon and GemStone software tools are presented, which implement the methodologies for developing power models and validating performance models, respectively.
University of Southampton
Walker, Matthew, James
77e58c74-1541-4ffc-9219-4c8c11248a2e
Walker, Matthew, James
77e58c74-1541-4ffc-9219-4c8c11248a2e
Merrett, Geoffrey
89b3a696-41de-44c3-89aa-b0aa29f54020

Walker, Matthew, James (2019) Hardware-validated performance and power modelling of heterogeneous multi-processing architectures. University of Southampton, Doctoral Thesis, 234pp.

Record type: Thesis (Doctoral)

Abstract

Modern processors are becoming increasingly more complex and utilise higher numbers of Heterogeneous Multi-Processing (HMP) cores. Energy-efficiency has become the primary design constraint in recent years, and improvements enable battery-powered devices to run longer and reduce the energy and cooling costs in data centres. Moreover, increased energy-efficiency enables greater peak performance under the thermal and power constraints, enabling innovative new uses and applications. Accurate run-time power estimations are critical in guiding online energy-saving techniques and energy-aware scheduling decisions to find the optimum performance, power and energy tradeoff. This thesis presents a statistically-rigorous methodology for developing accurate and stable empirical power models for providing run-time power estimations to a run-time manager (RTM) while considering thermal variation, coefficient stability, heteroscedasticity, robust model specification, and non-ideal voltage regulation. The novel methodology ensures that the models perform significantly more accurately across a wider range of workloads when compared with existing runtime power modelling methodologies, achieving average errors lower than four percent. Practical considerations and shortcomings in existing approaches are also identified and addressed.

Furthermore, the recent slowdown in technology scaling has forced researchers and engineers to rely on micro-architectural advances and system-level optimisations to drive performance improvement, the development of which is underpinned by simulation tools. However, such simulation tools inevitably have limitations and contain sources of error which, if not understood by the user, can lead to inaccurate results and incorrect conclusions. This thesis presents a methodology for evaluating CPU performance models and identifying specific sources of error, allowing such models to be improved; extended to other CPUs; validated after changes; and tested for suitability to a specific use case. These hardware-validated performance models are combined with the empirical power models to enable accurate and reliable performance, power and energy simulation.

Moreover, the Powmon and GemStone software tools are presented, which implement the methodologies for developing power models and validating performance models, respectively.

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Published date: June 2019

Identifiers

Local EPrints ID: 433537
URI: http://eprints.soton.ac.uk/id/eprint/433537
PURE UUID: f690e9ba-c533-4ea4-81f5-6703c477a5ec
ORCID for Matthew, James Walker: ORCID iD orcid.org/0000-0001-6368-3644
ORCID for Geoffrey Merrett: ORCID iD orcid.org/0000-0003-4980-3894

Catalogue record

Date deposited: 27 Aug 2019 16:30
Last modified: 19 Nov 2019 01:46

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Contributors

Author: Matthew, James Walker ORCID iD
Thesis advisor: Geoffrey Merrett ORCID iD

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