Ultra-low-power and variation-aware digital signal processing

Abstract

Internet of Things is a rapidly emerging technology that allows people and things to
be connected anywhere and any time, using any path or network. The ”things” in the
IoT applications need external power to perform any function. As a result, IoT devices
must offer superior power efficiency compared with previous digital applications. In
terms of power-saving techniques, voltage scaling is regarded as one of the most efficient
method. However, the aggressive scaling of the CMOS size and supply voltage have
posed a increase concern about circuit reliability. This thesis studies the effects of
process variation on the low-voltage digital signal processing circuits, with the aim to
develop efficient methods to further achieve power saving at the circuit-level and provide
corresponding cost-effective error mitigation techniques.

This thesis presents three major contributions. First of all, the analysis of process
variation on the adiabatic logic circuit (an energy recovery logic) is implemented and
bit-serial implementation is proposed as an efficient method to improve the energyefficiency
and robustness against variation. After that, our research emphasis in this
thesis is shifted to low power and reliable serial computing. The second contribution
demonstrates the advantages of serial computing on a FFT implementation in terms of
area minimisation, power-saving and energy-scalable operation. The third contribution
proposes several novel error-mitigation techniques for serial computing via path isolation,
variable latency or time borrowing. The FIR evaluation results show that the proposed
techniques can effectively mask or prevent timing errors with very low hardware cost and
make serial circuit as a promising candidate for power-efficient and reliable computing
in the IoT devices.

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