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Ultra-low-power and variation-aware digital signal processing

Ultra-low-power and variation-aware digital signal processing
Ultra-low-power and variation-aware digital signal processing
Internet of Things is a rapidly emerging technology that allows people and things to
be connected anywhere and any time, using any path or network. The ”things” in the
IoT applications need external power to perform any function. As a result, IoT devices
must offer superior power efficiency compared with previous digital applications. In
terms of power-saving techniques, voltage scaling is regarded as one of the most efficient
method. However, the aggressive scaling of the CMOS size and supply voltage have
posed a increase concern about circuit reliability. This thesis studies the effects of
process variation on the low-voltage digital signal processing circuits, with the aim to
develop efficient methods to further achieve power saving at the circuit-level and provide
corresponding cost-effective error mitigation techniques.

This thesis presents three major contributions. First of all, the analysis of process
variation on the adiabatic logic circuit (an energy recovery logic) is implemented and
bit-serial implementation is proposed as an efficient method to improve the energyefficiency
and robustness against variation. After that, our research emphasis in this
thesis is shifted to low power and reliable serial computing. The second contribution
demonstrates the advantages of serial computing on a FFT implementation in terms of
area minimisation, power-saving and energy-scalable operation. The third contribution
proposes several novel error-mitigation techniques for serial computing via path isolation,
variable latency or time borrowing. The FIR evaluation results show that the proposed
techniques can effectively mask or prevent timing errors with very low hardware cost and
make serial circuit as a promising candidate for power-efficient and reliable computing
in the IoT devices.
University of Southampton
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a

Lu, Yue (2019) Ultra-low-power and variation-aware digital signal processing. University of Southampton, Doctoral Thesis, 133pp.

Record type: Thesis (Doctoral)

Abstract

Internet of Things is a rapidly emerging technology that allows people and things to
be connected anywhere and any time, using any path or network. The ”things” in the
IoT applications need external power to perform any function. As a result, IoT devices
must offer superior power efficiency compared with previous digital applications. In
terms of power-saving techniques, voltage scaling is regarded as one of the most efficient
method. However, the aggressive scaling of the CMOS size and supply voltage have
posed a increase concern about circuit reliability. This thesis studies the effects of
process variation on the low-voltage digital signal processing circuits, with the aim to
develop efficient methods to further achieve power saving at the circuit-level and provide
corresponding cost-effective error mitigation techniques.

This thesis presents three major contributions. First of all, the analysis of process
variation on the adiabatic logic circuit (an energy recovery logic) is implemented and
bit-serial implementation is proposed as an efficient method to improve the energyefficiency
and robustness against variation. After that, our research emphasis in this
thesis is shifted to low power and reliable serial computing. The second contribution
demonstrates the advantages of serial computing on a FFT implementation in terms of
area minimisation, power-saving and energy-scalable operation. The third contribution
proposes several novel error-mitigation techniques for serial computing via path isolation,
variable latency or time borrowing. The FIR evaluation results show that the proposed
techniques can effectively mask or prevent timing errors with very low hardware cost and
make serial circuit as a promising candidate for power-efficient and reliable computing
in the IoT devices.

Text
Final Thesis - Version of Record
Available under License University of Southampton Thesis Licence.
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More information

Published date: May 2019

Identifiers

Local EPrints ID: 433539
URI: http://eprints.soton.ac.uk/id/eprint/433539
PURE UUID: cfd1f568-c2af-45d5-af7f-8a933ba4dd36

Catalogue record

Date deposited: 27 Aug 2019 16:30
Last modified: 27 Aug 2019 16:30

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Contributors

Author: Yue Lu
Thesis advisor: Tomasz Kazmierski

University divisions

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