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Fabrication and characterization of silicon nanowire FETs with coupled dopants induced quantum dot

Fabrication and characterization of silicon nanowire FETs with coupled dopants induced quantum dot
Fabrication and characterization of silicon nanowire FETs with coupled dopants induced quantum dot
Few dopants silicon transistor has been increasingly proposed in recent years, which provides a platform to understand the MOSFET scaling issues like threshold voltage shift, device performance non-consistent and dopant distribution fluctuations. The single and few dopants localized in silicon field effect transistor (FET) channel could also be used as the quantum dot (QD) for the single electron transistor (SET), which leads to an alternative way to achieve the quantum devices against the traditional method like structurally defined quantum dot. The modern fabrication technology like ion implantation and STM provide a more accurate method to define the single dopants in channel. However, the complex fabrication process makes these methods not practical. To overcome this technique challenge, Moraru and Tabe proposed the new fabrication method with spin-on dopants and selective doping to form the dopants cluster as a quantum dot. The study of the few dopants transistor also establishes the possibility for the future transistor with molecular and atomic scale.

In this work, I introduce two generations of silicon nanowire FETs (NW-FETs) with different device designs and fabrication processes with silicon on insulator (SOI) platform. The innovation introduced is the nanowire design with notch structure. The nanowire notch structure helps to confine the dopants without thinning the silicon layer to be sub5 nm, which reduces the complexity of fabrication process but increases the tolerance. The aim of these two generations is to develop the few dopants transistor with spin-on dopants. The rapid thermal annealing (RTA) is used for the first device batch. As for the second generation, the thermal diffusion is applied to form the clustered dopants and provide sufficient current flow at low temperature. The silicon dioxide is used as the doping mask in both experiments. The commercial device simulator software Silvaco is first used to prove the suitability of the NW-FET device design. Through the fabrication, hundreds of NW-FETs with various doping configurations are fabricated in parallel. Different Ebeam resist HSQ and ZEP are used successfully to transfer the nanowire design and the smallest width of nanowire after dry etch is around 50 nm.

For the first device generation, different NW-FETs with various device dimensions and doping configurations are measured. The short-channel effects are obtained from I-V characteristics including drain induced barrier lowing (DIBL) and gate induced drain leakage (GIDL) effects. By comparing the I-V performances of different devices at room temperature, the narrower and shorter the channel will contribute higher output current. However, the issue of the dopants freeze-out at low temperature make the device to be only measurable until 100K.

By analysing the feedbacks of the first generation device, both device design and fabrication process are upgraded for the second generation. The new spin-on dopants solution with higher concentration is used with the thermal diffusion method, which increases the doping concentration at source and drain. By comparing the device with intrinsic and doped channel, the difference between threshold voltage is analysed to be corresponding to the channel doping of approximate 5 × 1018 cm−3 . The QD Coulomb oscillation and Coulomb diamonds characteristics obtained at 5K indicate single electron tunnelling through localized QD. Through the analysis of the characteristics of QD, the formation of QD is due to the confined dopants under top gate are strongly coupled. The number of dopants in QD is estimated to be 4-5. Through the temperature dependent measurement, the electron transport follows the Mott variable hopping mechanism. The hopping distance is found to be 6.7 nm and the critical temperature is calculated to be 57K, which is consistent with the Arrhenius plot.

In a conclusion, the combination of thermally diffused spin-on dopants and notched nanowire successfully create the few dopants silicon NW-FET with clustered dopants. The standardized fabrication process is also established during the project. Through different measurements and analysis, the nature of QD is proved to be localized dopants deliberately doped selectively
University of Southampton
Tan, Zhencheng
e8fd0bd6-4a3f-4581-b32c-828c9dabc4c9
Tan, Zhencheng
e8fd0bd6-4a3f-4581-b32c-828c9dabc4c9
Chong, Harold
795aa67f-29e5-480f-b1bc-9bd5c0d558e1

Tan, Zhencheng (2019) Fabrication and characterization of silicon nanowire FETs with coupled dopants induced quantum dot. University of Southampton, Doctoral Thesis, 137pp.

Record type: Thesis (Doctoral)

Abstract

Few dopants silicon transistor has been increasingly proposed in recent years, which provides a platform to understand the MOSFET scaling issues like threshold voltage shift, device performance non-consistent and dopant distribution fluctuations. The single and few dopants localized in silicon field effect transistor (FET) channel could also be used as the quantum dot (QD) for the single electron transistor (SET), which leads to an alternative way to achieve the quantum devices against the traditional method like structurally defined quantum dot. The modern fabrication technology like ion implantation and STM provide a more accurate method to define the single dopants in channel. However, the complex fabrication process makes these methods not practical. To overcome this technique challenge, Moraru and Tabe proposed the new fabrication method with spin-on dopants and selective doping to form the dopants cluster as a quantum dot. The study of the few dopants transistor also establishes the possibility for the future transistor with molecular and atomic scale.

In this work, I introduce two generations of silicon nanowire FETs (NW-FETs) with different device designs and fabrication processes with silicon on insulator (SOI) platform. The innovation introduced is the nanowire design with notch structure. The nanowire notch structure helps to confine the dopants without thinning the silicon layer to be sub5 nm, which reduces the complexity of fabrication process but increases the tolerance. The aim of these two generations is to develop the few dopants transistor with spin-on dopants. The rapid thermal annealing (RTA) is used for the first device batch. As for the second generation, the thermal diffusion is applied to form the clustered dopants and provide sufficient current flow at low temperature. The silicon dioxide is used as the doping mask in both experiments. The commercial device simulator software Silvaco is first used to prove the suitability of the NW-FET device design. Through the fabrication, hundreds of NW-FETs with various doping configurations are fabricated in parallel. Different Ebeam resist HSQ and ZEP are used successfully to transfer the nanowire design and the smallest width of nanowire after dry etch is around 50 nm.

For the first device generation, different NW-FETs with various device dimensions and doping configurations are measured. The short-channel effects are obtained from I-V characteristics including drain induced barrier lowing (DIBL) and gate induced drain leakage (GIDL) effects. By comparing the I-V performances of different devices at room temperature, the narrower and shorter the channel will contribute higher output current. However, the issue of the dopants freeze-out at low temperature make the device to be only measurable until 100K.

By analysing the feedbacks of the first generation device, both device design and fabrication process are upgraded for the second generation. The new spin-on dopants solution with higher concentration is used with the thermal diffusion method, which increases the doping concentration at source and drain. By comparing the device with intrinsic and doped channel, the difference between threshold voltage is analysed to be corresponding to the channel doping of approximate 5 × 1018 cm−3 . The QD Coulomb oscillation and Coulomb diamonds characteristics obtained at 5K indicate single electron tunnelling through localized QD. Through the analysis of the characteristics of QD, the formation of QD is due to the confined dopants under top gate are strongly coupled. The number of dopants in QD is estimated to be 4-5. Through the temperature dependent measurement, the electron transport follows the Mott variable hopping mechanism. The hopping distance is found to be 6.7 nm and the critical temperature is calculated to be 57K, which is consistent with the Arrhenius plot.

In a conclusion, the combination of thermally diffused spin-on dopants and notched nanowire successfully create the few dopants silicon NW-FET with clustered dopants. The standardized fabrication process is also established during the project. Through different measurements and analysis, the nature of QD is proved to be localized dopants deliberately doped selectively

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Published date: April 2019

Identifiers

Local EPrints ID: 433554
URI: http://eprints.soton.ac.uk/id/eprint/433554
PURE UUID: ca4389a2-5b61-477f-867e-fa40f06b1908
ORCID for Harold Chong: ORCID iD orcid.org/0000-0002-7110-5761

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Date deposited: 27 Aug 2019 16:30
Last modified: 28 Aug 2019 00:33

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Contributors

Author: Zhencheng Tan
Thesis advisor: Harold Chong ORCID iD

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