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Cost-efficient delay-fault sensors for ageing prediction

Cost-efficient delay-fault sensors for ageing prediction
Cost-efficient delay-fault sensors for ageing prediction
Aggressive technology scaling has accelerated the ageing of CMOS devices. Ageing refers to a slow progressive degradation in the performance of MOS transistors. Consequently, the speed of a chip can significantly degrade over time; this results in delay faults. Dynamic reliability management schemes have been proposed to assure an IC's lifetime reliability. Such schemes are typically based on the use of ageing sensors to predict a circuit's failure before the actual errors appear. Existing ageing sensors are usually placed on the circuit's longest delay paths, which are deemed to be the most vulnerable to delay faults. Such an approach is very costly and may be infeasible in today's complex designs that typically have a large number of long delay paths that need to be monitored. Existing ageing models are proposed to estimate the lifetime of an IC before it's fabrication. However, The result is inaccurate without considering the actual operating conditions of the circuit. Various ageing mitigation technique has been proposed to extend the lifetime of an IC. A trade-off between lifetime and performance usually achieves such approaches. Such sacrifices are reluctant.

We propose two sensors, Parity Check Circuit (PCC) and Differential Multiple Error Detection Sensor (DMEDS), for cost-efficient delay fault monitoring. Both of those two sensors can monitor multiple paths simultaneously, which reduces the number of sensors significantly. The PCC has been designed and verified in a 65nm technology. Our results indicate that using the proposed sensor for delay fault monitoring in a 32-bit MIPS can lead to a significant saving in the area and power overheads, compared to the use of canary flip-flops [40]: by two-thirds and one-third, respectively. The DMEDS has been designed at transistor level in a 32 nm and 90 nm CMOS technology and verified at the system level. Our results indicate that the use of the proposed sensor for delay fault monitoring across ten paths can lead to a significant saving in area overhead compared to Razor [29], and Canary [40]: 87.59%, 77.67%, respectively. We also propose an idea of lifetime prediction system, and it compares the data with reference to analysis the ageing of the device. Our results indicate that the use of the proposed system for lifetime prediction system can accurately estimate the lifetime of the IC compared with the data from the ageing model. The error is controlled within 5% with limited reference data.
University of Southampton
Sai, Gaole
6fc26dc4-af9d-4409-9de4-7b639846da85
Sai, Gaole
6fc26dc4-af9d-4409-9de4-7b639846da85
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Sai, Gaole (2018) Cost-efficient delay-fault sensors for ageing prediction. University of Southampton, Doctoral Thesis, 145pp.

Record type: Thesis (Doctoral)

Abstract

Aggressive technology scaling has accelerated the ageing of CMOS devices. Ageing refers to a slow progressive degradation in the performance of MOS transistors. Consequently, the speed of a chip can significantly degrade over time; this results in delay faults. Dynamic reliability management schemes have been proposed to assure an IC's lifetime reliability. Such schemes are typically based on the use of ageing sensors to predict a circuit's failure before the actual errors appear. Existing ageing sensors are usually placed on the circuit's longest delay paths, which are deemed to be the most vulnerable to delay faults. Such an approach is very costly and may be infeasible in today's complex designs that typically have a large number of long delay paths that need to be monitored. Existing ageing models are proposed to estimate the lifetime of an IC before it's fabrication. However, The result is inaccurate without considering the actual operating conditions of the circuit. Various ageing mitigation technique has been proposed to extend the lifetime of an IC. A trade-off between lifetime and performance usually achieves such approaches. Such sacrifices are reluctant.

We propose two sensors, Parity Check Circuit (PCC) and Differential Multiple Error Detection Sensor (DMEDS), for cost-efficient delay fault monitoring. Both of those two sensors can monitor multiple paths simultaneously, which reduces the number of sensors significantly. The PCC has been designed and verified in a 65nm technology. Our results indicate that using the proposed sensor for delay fault monitoring in a 32-bit MIPS can lead to a significant saving in the area and power overheads, compared to the use of canary flip-flops [40]: by two-thirds and one-third, respectively. The DMEDS has been designed at transistor level in a 32 nm and 90 nm CMOS technology and verified at the system level. Our results indicate that the use of the proposed sensor for delay fault monitoring across ten paths can lead to a significant saving in area overhead compared to Razor [29], and Canary [40]: 87.59%, 77.67%, respectively. We also propose an idea of lifetime prediction system, and it compares the data with reference to analysis the ageing of the device. Our results indicate that the use of the proposed system for lifetime prediction system can accurately estimate the lifetime of the IC compared with the data from the ageing model. The error is controlled within 5% with limited reference data.

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Cost-effcient Delay-Fault Sensors for Ageing Prediction - Version of Record
Available under License University of Southampton Thesis Licence.
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Published date: November 2018

Identifiers

Local EPrints ID: 438576
URI: http://eprints.soton.ac.uk/id/eprint/438576
PURE UUID: 163e87b4-1719-4957-95fe-aae17b32f478
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 17 Mar 2020 17:33
Last modified: 13 Dec 2021 02:34

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Contributors

Author: Gaole Sai
Thesis advisor: Mark Zwolinski ORCID iD

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