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An investigation into ageing-resilient processor design

An investigation into ageing-resilient processor design
An investigation into ageing-resilient processor design
Microprocessors offer the ability for fast and reliable processing and are indispensable in many general and specific computing systems in different disciplines. In the past decades, CMOS technology size has progressively decreased, which has resulted in devices with smaller areas and lower power consumptions. However, side effects like ageing become more critical at smaller technology sizes, and this bottleneck challenges further improvements in CMOS technology. The main challenge of advanced technologies is at the physical level of the CMOS device, in which the device-level response time degrades over time due to higher-level stress (e.g. workload from a software).

Advanced materials that cope with ageing effects could take years to be developed; therefore, this thesis focuses on the stress that is propagated from software-level and explores techniques to mitigate the ageing behaviour by reducing stress from its source. The first part of the thesis targets single-core processors. We present a novel technique to mitigate the bias temperature instability (BTI) ageing effects on microprocessors.

After intensive analysis of ageing and its sources from the program level to the device level, we found that an application may stress the critical paths of a circuit in a way that may have half of the nodes always negative BTI stressed, while the second half are positive BTI stressed. To mitigate this behaviour, we propose an application-level solution to reverse the stress and put the processor nodes into a relaxed mode.

In the second part of the thesis, we investigate how multi-core processors could be used to mitigate BTI ageing effects by using the fact that idleness is adverse to a processor core at high temperatures. We show that it is necessary to run an anti-ageing program on the idle core in order to relax the stress or proactively avoid the stress generated by a high-level application by analysing the workload and develop a learning model to estimate the stress and its distribution on the multi-core processor. Subsequently, this model is used in a frequency regulator to dynamically adjust the frequencies of the core based on the estimated stress. Results show that by applying the proposed techniques,
the ageing stress could be reduced by a half.
University of Southampton
Abbas, Haider Muhi
df25f48a-4b00-4913-8456-d80a0c31ac10
Abbas, Haider Muhi
df25f48a-4b00-4913-8456-d80a0c31ac10
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33

Abbas, Haider Muhi (2018) An investigation into ageing-resilient processor design. University of Southampton, Doctoral Thesis, 194pp.

Record type: Thesis (Doctoral)

Abstract

Microprocessors offer the ability for fast and reliable processing and are indispensable in many general and specific computing systems in different disciplines. In the past decades, CMOS technology size has progressively decreased, which has resulted in devices with smaller areas and lower power consumptions. However, side effects like ageing become more critical at smaller technology sizes, and this bottleneck challenges further improvements in CMOS technology. The main challenge of advanced technologies is at the physical level of the CMOS device, in which the device-level response time degrades over time due to higher-level stress (e.g. workload from a software).

Advanced materials that cope with ageing effects could take years to be developed; therefore, this thesis focuses on the stress that is propagated from software-level and explores techniques to mitigate the ageing behaviour by reducing stress from its source. The first part of the thesis targets single-core processors. We present a novel technique to mitigate the bias temperature instability (BTI) ageing effects on microprocessors.

After intensive analysis of ageing and its sources from the program level to the device level, we found that an application may stress the critical paths of a circuit in a way that may have half of the nodes always negative BTI stressed, while the second half are positive BTI stressed. To mitigate this behaviour, we propose an application-level solution to reverse the stress and put the processor nodes into a relaxed mode.

In the second part of the thesis, we investigate how multi-core processors could be used to mitigate BTI ageing effects by using the fact that idleness is adverse to a processor core at high temperatures. We show that it is necessary to run an anti-ageing program on the idle core in order to relax the stress or proactively avoid the stress generated by a high-level application by analysing the workload and develop a learning model to estimate the stress and its distribution on the multi-core processor. Subsequently, this model is used in a frequency regulator to dynamically adjust the frequencies of the core based on the estimated stress. Results show that by applying the proposed techniques,
the ageing stress could be reduced by a half.

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An Investigation into Ageing-Resilient Processor Design - Version of Record
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Published date: October 2018

Identifiers

Local EPrints ID: 438577
URI: http://eprints.soton.ac.uk/id/eprint/438577
PURE UUID: 5479b6b1-0340-4a1c-b8a5-e085c6b8ec29
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226

Catalogue record

Date deposited: 17 Mar 2020 17:33
Last modified: 13 Dec 2021 03:06

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Contributors

Author: Haider Muhi Abbas
Thesis advisor: Basel Halak ORCID iD

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