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Hardware architecture for real-time EEG-based functional brain connectivity parameter extraction

Hardware architecture for real-time EEG-based functional brain connectivity parameter extraction
Hardware architecture for real-time EEG-based functional brain connectivity parameter extraction
In this work, we proposed a novel architecture for real-time quantitative characterization of functional brain connectivity networks derived from Electroencephalogram (EEG). It consists of two main parts - calculation of Phase Lag Index (PLI) to form the functional connectivity networks and the extraction of a set of graph-theoretic parameters to quantitatively characterize these networks. The architecture was developed for a 19-channel EEG system. The system can calculate all the functional connectivity parameters in a total time of 131µs, utilizes 71% logic resources, and shows 51.84 mW dynamic power consumption at 22.16 MHz operation frequency when implemented in a Stratix IV EP4SGX230K FPGA. Our analysis also showed that the system occupies an area equivalent to approximately 937K 2-input NAND gates, with an estimated power consumption of 39.3 mW at 0.9 V supply using a 90 nm CMOS Application Specific Integrated Circuit (ASIC) technology.
EEG, FPGA, functional connectivity, graph connectivity, phase lag index, real-time processing
1741-2552
Nuno, Rafael Angel Gutierrez
0d732031-1fc9-40bf-b91f-3af547ea9b54
Chung, Chi Hang Raphael
b803c9bf-f7a2-4730-82d0-30f18a8f69ea
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd
Nuno, Rafael Angel Gutierrez
0d732031-1fc9-40bf-b91f-3af547ea9b54
Chung, Chi Hang Raphael
b803c9bf-f7a2-4730-82d0-30f18a8f69ea
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd

Nuno, Rafael Angel Gutierrez, Chung, Chi Hang Raphael and Maharatna, Koushik (2021) Hardware architecture for real-time EEG-based functional brain connectivity parameter extraction. Journal of Neural Engineering, 18 (3), [036012]. (doi:10.1088/1741-2552/abd462).

Record type: Article

Abstract

In this work, we proposed a novel architecture for real-time quantitative characterization of functional brain connectivity networks derived from Electroencephalogram (EEG). It consists of two main parts - calculation of Phase Lag Index (PLI) to form the functional connectivity networks and the extraction of a set of graph-theoretic parameters to quantitatively characterize these networks. The architecture was developed for a 19-channel EEG system. The system can calculate all the functional connectivity parameters in a total time of 131µs, utilizes 71% logic resources, and shows 51.84 mW dynamic power consumption at 22.16 MHz operation frequency when implemented in a Stratix IV EP4SGX230K FPGA. Our analysis also showed that the system occupies an area equivalent to approximately 937K 2-input NAND gates, with an estimated power consumption of 39.3 mW at 0.9 V supply using a 90 nm CMOS Application Specific Integrated Circuit (ASIC) technology.

Text
Gutierrez+Nuno+et+al_2020_J._Neural_Eng._10.1088_1741-2552_abd462 - Accepted Manuscript
Restricted to Repository staff only until 9 March 2022.
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More information

Accepted/In Press date: 16 December 2020
e-pub ahead of print date: 9 March 2021
Keywords: EEG, FPGA, functional connectivity, graph connectivity, phase lag index, real-time processing

Identifiers

Local EPrints ID: 447096
URI: http://eprints.soton.ac.uk/id/eprint/447096
ISSN: 1741-2552
PURE UUID: 626ddbf3-2093-493e-94cd-13d3df1044e1
ORCID for Rafael Angel Gutierrez Nuno: ORCID iD orcid.org/0000-0002-8226-4725

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Date deposited: 03 Mar 2021 17:31
Last modified: 17 Apr 2021 01:55

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Contributors

Author: Rafael Angel Gutierrez Nuno ORCID iD
Author: Chi Hang Raphael Chung
Author: Koushik Maharatna

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