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Narrow slot fully-crystalline accumulation modulator for low-power optoelectronic interconnection

Narrow slot fully-crystalline accumulation modulator for low-power optoelectronic interconnection
Narrow slot fully-crystalline accumulation modulator for low-power optoelectronic interconnection
The information and telecommunication industry relies heavily on the opto-electronic(OE) modulator link between electronic computation and optical data transmission. Asglobal data consumption has increased, the bandwidth, efficiency and cost demands placed upon OE modulators (in data centres for example) has also increased. OE modulators based on a silicon photonic platform have the potential to meet these bandwidthand efficiency demands, whilst remaining cost effective and industrially scalable due to their compatibility with conventional complemetary metal-oxide semiconductor (CMOS) fabrication processes.The goal of this PhD project was to design and demonstrate a new type of energy efficiency, high-speed, fully-crystalline-Si (c-Si) modulator that could potentially answer the industry needs. To this end, in this thesis I present two new c-Si accumulation plasma dispersion effect (PDE) modulator designs. The critical OE component of these designs is, on the one hand, a bi-planar, horizontal-slot fin-waveguide on a double-silicon on-insulator (SOI) platform, and on the other hand, a planar, partially recrystallised,vertical-slot rib-waveguide. The key contributions I have made are (1) the development of a unique fabrication process involving anisotropic wet etching of mirrored Si crystal planes to realise the low-loss(0.85dB/mm) bi-planar, horizontal-slot fin-waveguide for use in an OE modulator, and(2) the fabrication of an efficient, fully-c-Si accumulation modulator with switching speed of 25Gb/s and modulation efficiency of 1.53V·π. This modulator is the first demonstration of a uniquely designed modulator architecture which, with optimization, has the potential the genuinely address the industry demand for an energy-efficient, high-speed CMOS compatible OE modulator.
University of Southampton
Byers, James
124172c9-0709-4cb9-992e-acedc2eb02bf
Byers, James
124172c9-0709-4cb9-992e-acedc2eb02bf
Saito, Shinichi
14a5d20b-055e-4f48-9dda-267e88bd3fdc

Byers, James (2020) Narrow slot fully-crystalline accumulation modulator for low-power optoelectronic interconnection. Doctoral Thesis, 139pp.

Record type: Thesis (Doctoral)

Abstract

The information and telecommunication industry relies heavily on the opto-electronic(OE) modulator link between electronic computation and optical data transmission. Asglobal data consumption has increased, the bandwidth, efficiency and cost demands placed upon OE modulators (in data centres for example) has also increased. OE modulators based on a silicon photonic platform have the potential to meet these bandwidthand efficiency demands, whilst remaining cost effective and industrially scalable due to their compatibility with conventional complemetary metal-oxide semiconductor (CMOS) fabrication processes.The goal of this PhD project was to design and demonstrate a new type of energy efficiency, high-speed, fully-crystalline-Si (c-Si) modulator that could potentially answer the industry needs. To this end, in this thesis I present two new c-Si accumulation plasma dispersion effect (PDE) modulator designs. The critical OE component of these designs is, on the one hand, a bi-planar, horizontal-slot fin-waveguide on a double-silicon on-insulator (SOI) platform, and on the other hand, a planar, partially recrystallised,vertical-slot rib-waveguide. The key contributions I have made are (1) the development of a unique fabrication process involving anisotropic wet etching of mirrored Si crystal planes to realise the low-loss(0.85dB/mm) bi-planar, horizontal-slot fin-waveguide for use in an OE modulator, and(2) the fabrication of an efficient, fully-c-Si accumulation modulator with switching speed of 25Gb/s and modulation efficiency of 1.53V·π. This modulator is the first demonstration of a uniquely designed modulator architecture which, with optimization, has the potential the genuinely address the industry demand for an energy-efficient, high-speed CMOS compatible OE modulator.

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Published date: July 2020

Identifiers

Local EPrints ID: 447367
URI: http://eprints.soton.ac.uk/id/eprint/447367
PURE UUID: 37a4d231-ddac-4157-9dc7-281a99dd64a1
ORCID for Shinichi Saito: ORCID iD orcid.org/0000-0003-1539-1182

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Date deposited: 10 Mar 2021 17:35
Last modified: 23 Jul 2022 02:05

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Contributors

Author: James Byers
Thesis advisor: Shinichi Saito ORCID iD

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