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A globally wireless locally wired hybrid clock distribution network for many-core systems

A globally wireless locally wired hybrid clock distribution network for many-core systems
A globally wireless locally wired hybrid clock distribution network for many-core systems
Modern ICs are now facing critical issues on generating power-efficient and globally interconnected clock networks, as the clock distribution network might contribute to more than 50% of the overall power consumption. Besides, due to the increasing wire delay caused by shrinking interconnect dimensions, synchronous many-core systems are now facing challenges such as to propagate high-frequency clock signals across the chip with limited power budget. Delivering a clock with low uncertainties across active dies with large chip density has also become one of the major tasks using conventional metallic
interconnects. This thesis presents a novel architecture and comprehensive evaluations for a power efficient and extremely low-delay approach using hybrid wire-wireless clock distribution network (CDN). The proposed hybrid CDN adopts wireless on-chip clock transmitters and receivers for broadcasting the clock signal globally. It then incorporates with conventional metal-based clock tree or mesh for local clock distribution. Comparisons between the proposed approach and two baseline architectures, namely a full fan-out tree and a global tree local mesh (TLM) structure, have been presented. Also, an accurate mathematical model with interconnect RLC parameters for the local clock distribution is employed.
The hybrid CDN has shown its superiority in terms of low clock delay, low clock skew and high energy efficiency compared with conventional solutions, which is evaluated via an industrial standard Arm Mali G77 GPU case study. Experimental results indicate that the proposed clock distribution network can achieve a significant global delay reduction of up to 28.8%. Also, on average, an up to 62.8% and 42.7% reduction in clock skew and power consumption, are identified, respectively, in our proposed test bench. Hence, our proposed approach offers a promising solution to clock distribution in future many-core integrated circuits, especially for high-performance systems.
University of Southampton
Ding, Qian
c7228f74-158a-44b9-b875-3096d24258e8
Ding, Qian
c7228f74-158a-44b9-b875-3096d24258e8
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53

Ding, Qian (2021) A globally wireless locally wired hybrid clock distribution network for many-core systems. University of Southampton, Doctoral Thesis, 161pp.

Record type: Thesis (Doctoral)

Abstract

Modern ICs are now facing critical issues on generating power-efficient and globally interconnected clock networks, as the clock distribution network might contribute to more than 50% of the overall power consumption. Besides, due to the increasing wire delay caused by shrinking interconnect dimensions, synchronous many-core systems are now facing challenges such as to propagate high-frequency clock signals across the chip with limited power budget. Delivering a clock with low uncertainties across active dies with large chip density has also become one of the major tasks using conventional metallic
interconnects. This thesis presents a novel architecture and comprehensive evaluations for a power efficient and extremely low-delay approach using hybrid wire-wireless clock distribution network (CDN). The proposed hybrid CDN adopts wireless on-chip clock transmitters and receivers for broadcasting the clock signal globally. It then incorporates with conventional metal-based clock tree or mesh for local clock distribution. Comparisons between the proposed approach and two baseline architectures, namely a full fan-out tree and a global tree local mesh (TLM) structure, have been presented. Also, an accurate mathematical model with interconnect RLC parameters for the local clock distribution is employed.
The hybrid CDN has shown its superiority in terms of low clock delay, low clock skew and high energy efficiency compared with conventional solutions, which is evaluated via an industrial standard Arm Mali G77 GPU case study. Experimental results indicate that the proposed clock distribution network can achieve a significant global delay reduction of up to 28.8%. Also, on average, an up to 62.8% and 42.7% reduction in clock skew and power consumption, are identified, respectively, in our proposed test bench. Hence, our proposed approach offers a promising solution to clock distribution in future many-core integrated circuits, especially for high-performance systems.

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Published date: February 2021

Identifiers

Local EPrints ID: 448518
URI: http://eprints.soton.ac.uk/id/eprint/448518
PURE UUID: b16dc213-630c-47bf-87cd-d4f9f2bf4f66

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Date deposited: 23 Apr 2021 16:35
Last modified: 23 Apr 2021 16:35

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Contributors

Author: Qian Ding
Thesis advisor: Terrence Mak

University divisions

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