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A 77-dB DR 16-Ch 2nd-order Delta-Delta sigma neural recording chip with 0.0077mm2/Ch

A 77-dB DR 16-Ch 2nd-order Delta-Delta sigma neural recording chip with 0.0077mm2/Ch
A 77-dB DR 16-Ch 2nd-order Delta-Delta sigma neural recording chip with 0.0077mm2/Ch
This paper presents a scalable 16-channel neural recording chip enabling simultaneous acquisition of action-potentials (APs), local-field potentials (LFPs), electrode DC offsets (EDOs) and stimulation artifacts (SAs) without saturation. By combining a DC-coupled Δ-ΔΣ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077mm2 per channel, an input-referred noise of 5.53±0.36 μVrms in the AP band and 2.88±0.18 μVrms in the LFP band, a dynamic range (DR) of 77dB, an EDO tolerance of ±70mV and an input impedance of 283MΩ. The chip has been validated in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultrahigh-density neural probes for large-scale electrophysiology.
Wang, Shiwei
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Ballini, Marco
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Yang, Xiaolin
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Sawigun, Chutham
c00fdbab-2b5d-4419-842c-616173a6c168
Weijers, Jan-Willem
67674143-0bb7-4fd5-9654-6e297ba56641
Biswas, Dwaipayan
e22da6d8-e707-4c4a-8b07-85f15d5ee983
Mora Lopez, Carolina
205c7c03-ec14-463e-84c6-a46b12e3177c
Wang, Shiwei
97433cb6-7752-4c68-89f8-933f233d8642
Ballini, Marco
5ce563dd-6818-4688-b799-1df93ccf5df1
Yang, Xiaolin
2ef568bb-2b83-4b4f-aa5c-488855fca2b2
Sawigun, Chutham
c00fdbab-2b5d-4419-842c-616173a6c168
Weijers, Jan-Willem
67674143-0bb7-4fd5-9654-6e297ba56641
Biswas, Dwaipayan
e22da6d8-e707-4c4a-8b07-85f15d5ee983
Mora Lopez, Carolina
205c7c03-ec14-463e-84c6-a46b12e3177c

Wang, Shiwei, Ballini, Marco, Yang, Xiaolin, Sawigun, Chutham, Weijers, Jan-Willem, Biswas, Dwaipayan and Mora Lopez, Carolina (2021) A 77-dB DR 16-Ch 2nd-order Delta-Delta sigma neural recording chip with 0.0077mm2/Ch. 2021 Symposium on VLSI Circuits. 13 - 19 Jun 2021.

Record type: Conference or Workshop Item (Paper)

Abstract

This paper presents a scalable 16-channel neural recording chip enabling simultaneous acquisition of action-potentials (APs), local-field potentials (LFPs), electrode DC offsets (EDOs) and stimulation artifacts (SAs) without saturation. By combining a DC-coupled Δ-ΔΣ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077mm2 per channel, an input-referred noise of 5.53±0.36 μVrms in the AP band and 2.88±0.18 μVrms in the LFP band, a dynamic range (DR) of 77dB, an EDO tolerance of ±70mV and an input impedance of 283MΩ. The chip has been validated in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultrahigh-density neural probes for large-scale electrophysiology.

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C13_5 - Accepted Manuscript
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More information

Accepted/In Press date: 31 March 2021
Published date: 28 July 2021
Venue - Dates: 2021 Symposium on VLSI Circuits, 2021-06-13 - 2021-06-19

Identifiers

Local EPrints ID: 450079
URI: http://eprints.soton.ac.uk/id/eprint/450079
PURE UUID: d4390fb6-08f3-42f2-9ae8-a73fdc5bf68a
ORCID for Shiwei Wang: ORCID iD orcid.org/0000-0002-5450-2108

Catalogue record

Date deposited: 08 Jul 2021 16:32
Last modified: 17 Sep 2021 02:02

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Contributors

Author: Shiwei Wang ORCID iD
Author: Marco Ballini
Author: Xiaolin Yang
Author: Chutham Sawigun
Author: Jan-Willem Weijers
Author: Dwaipayan Biswas
Author: Carolina Mora Lopez

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