A compact chopper stabilized Δ-ΔΣ neural readout IC with input impedance boosting

Abstract

This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled - architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077 mm2 per channel, an input-referred noise of 5.53 ± 0.36 µVrms in the action potential band and 2.88 ± 0.18 µVrms in the local field potential band, a dynamic range of 77 dB, an electrode-DC-offset tolerance of ±70 mV and an input impedance of 663 M. To validate this neural readout architecture, we fabricated a 16-channel proof of-concept IC and validated it in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology

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ORCID for Shiwei Wang: orcid.org/0000-0002-5450-2108

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