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Conduction channel configuration controlled digital and analog response in TiO2-based inorganic memristive artificial synapses

Conduction channel configuration controlled digital and analog response in TiO2-based inorganic memristive artificial synapses
Conduction channel configuration controlled digital and analog response in TiO2-based inorganic memristive artificial synapses
The operating current regime is found to play a key role in determining the synaptic characteristic of memristor devices. A conduction channel that is formed using high current compliance prior to the synaptic operation results in digital behavior; the high current stimulus forms a complete conductive filament connecting the cathode and anode, and the high electric field promotes abrupt redox reactions during potentiation and depression pulsing schemes. Conversely, the conduction can be reconfigured to produce a filamentary-homogeneous hybrid channel by utilizing the low current stimulus, and this configuration enables the occurrence of analog behavior. The capabilities of memristors showing programmable digital-to-analog or analog-to-digital transformation open a wide range of applications in electronics. We propose a conduction mechanism to explain this phenomenon.
Analog memristor technologies offer promising potential for in-memory computing applications.1 In-memory computing is a state-of-the-art computer architecture that envisages data processing in the memory unit and thus overcomes data latency between memory and central processing units.1 A memristor device has a facile top-electrode/metal oxide (switching layer)/bottom-electrode sandwiched architectonic rendering ultra-high-density circuits;2 the recent effort has successfully fabricated cross-bar arrays having sub-15 nm cells.3 Moreover, such a small dimension and its low power operation could realize memristor–neuron coupling to enable the silicon–brain interface.4,5
Several physical and chemical mechanisms have been proposed to explain the electron conduction in the memory cell, such as those based on metallic diffusion (electrochemical metallization), valence change, thermo-chemical, and interfacial coupling.6–8 A valence change memristor is controlled by an electric field that induces the formation and rupture of oxygen vacancy filaments to switch the device On (state 1) and Off (state 0), respectively, also called memristive behavior.9 The formation of the filament is initiated by the creation of oxygen vacancies by ionizing the oxygen from the lattice of the oxide switching layer, and these vacancies grow from the cathode to anode while the oxygen ions drift to and are oxidized at the anode/switching layer interface; the electrons, then, can easily flow through this filament, enabling the device in a low resistance state (LRS, state 1).10 Conversely, the filament can be ruptured by re-ionizing the oxygen at the anode/switching layer interface to recombine with the vacancies, creating a conduction gap between the electrode and remnant of the filament and, hence, switching the device to a high resistance state (HRS, state 0).10
Furthermore, the formation and rupture of the filaments can be used by an electric stimulus having short pulses and small amplitude to exhibit multiple states (states beyond 1 and 0); consequently, the device can perform an analogous gradual rise and fall of conductance.11 The gradual rise and fall of the conductance are called potentiation and depression, respectively, mimicking the mammalian brain's analogous synaptic weight response.12 However, the fabrication of analog memristors requires careful design and optimization, which makes the manufacturing process greatly challenging; this is because memristor devices often show digital behavior instead of analog, where the conductance change occurs abruptly.13
Various designs have been proposed to achieve a reliable synaptic response but mostly focus on programming the pulse scheme11 and engineering the switching materials such as bi-layering,14 doping,15 embedding with nanocrystals,16 and surface modification.17 These methods could indeed improve the synaptic response; however, the fundamental question of the relationship between the electron conduction and the structure of the filaments determining such analog and digital behavior in memristor devices is still less examined. In this work, we investigate the conduction channel configuration at the interface responsible for dictating the analog and digital response of the memristors. We explain the occurrence of digital-to-analog transformation in the device, and the conduction mechanism is also proposed by studying the phenomenon observed in devices having different thicknesses.
The device architecture and measurement setup are depicted in Figs. 1(a) and 1(b), respectively. A 15 nm TiN bottom electrode (BE) was deposited onto a Pt/Ti-coated Si-wafer substrate employing the atomic layer deposition technique. TiO2 switching layer films with thicknesses of 16 and 25 nm were deposited onto the bottom electrode. Hereafter, TiN/Ti bilayer top electrodes (TEs) having a diameter of 250 µm were patterned onto the TiO2 films using a metal shadow mask. The sheet resistance of the TiN electrodes is found to be less than 19 Ω/sq. The thicknesses of TiN and Ti are 50 and 15 nm, respectively. The TiO2, TiN, and Ti films were deposited using a DC sputtering system from a Ti target in a mixture of Ar/O2, Ar/N2, and Ar ambience, respectively. The devices made with 16 and 25 nm thick TiO2 films were denoted as D16 and D25, respectively. The electrical characteristics were investigated using an Agilent B1500A semiconductor analyzer. A voltage bias was applied to the top electrode while the bottom electrode was grounded; a current compliance (CC) was used during the positive bias voltage sweep to avoid permanent breakdown. For DC sweep, a negative bias of −1.4 V was used for all devices to switch the device Off. In the case of synaptic measurement, AC pulse schemes were used to induce the response by applying pulse amplitudes of −1.2 and 1 V for depression and potentiation, respectively, with a pulse width of 20 µs. Meanwhile, the pulse read was conducted using an amplitude of 0.1 V with a width of 1 ms. An epoch consists of 500 pulses of depression (D) and 500 pulses of potentiation (P). Note that the synaptic response test was conducted after several switching cycles. The element profile and defect were measured by x-ray photoelectron spectroscopy (XPS, PHI Quantera SXM).
2166-532X
Simanjuntak, Firman
a5b8dd07-002c-4520-9f67-2dc20d2ff0d5
Hsu, Chun-Ling
41f166b8-e782-4434-98dc-c8f368a66ece
Abbey, Thomas
64fcf5bd-e20e-4fb8-9ec4-391ad8a0a7a8
Hsu, Chun-Ling
41f166b8-e782-4434-98dc-c8f368a66ece
Simanjuntak, Firman
a5b8dd07-002c-4520-9f67-2dc20d2ff0d5
Hsu, Chun-Ling
41f166b8-e782-4434-98dc-c8f368a66ece
Abbey, Thomas
64fcf5bd-e20e-4fb8-9ec4-391ad8a0a7a8
Hsu, Chun-Ling
41f166b8-e782-4434-98dc-c8f368a66ece

Simanjuntak, Firman, Hsu, Chun-Ling, Abbey, Thomas and Hsu, Chun-Ling (2021) Conduction channel configuration controlled digital and analog response in TiO2-based inorganic memristive artificial synapses. APL Materials, [121103].

Record type: Article

Abstract

The operating current regime is found to play a key role in determining the synaptic characteristic of memristor devices. A conduction channel that is formed using high current compliance prior to the synaptic operation results in digital behavior; the high current stimulus forms a complete conductive filament connecting the cathode and anode, and the high electric field promotes abrupt redox reactions during potentiation and depression pulsing schemes. Conversely, the conduction can be reconfigured to produce a filamentary-homogeneous hybrid channel by utilizing the low current stimulus, and this configuration enables the occurrence of analog behavior. The capabilities of memristors showing programmable digital-to-analog or analog-to-digital transformation open a wide range of applications in electronics. We propose a conduction mechanism to explain this phenomenon.
Analog memristor technologies offer promising potential for in-memory computing applications.1 In-memory computing is a state-of-the-art computer architecture that envisages data processing in the memory unit and thus overcomes data latency between memory and central processing units.1 A memristor device has a facile top-electrode/metal oxide (switching layer)/bottom-electrode sandwiched architectonic rendering ultra-high-density circuits;2 the recent effort has successfully fabricated cross-bar arrays having sub-15 nm cells.3 Moreover, such a small dimension and its low power operation could realize memristor–neuron coupling to enable the silicon–brain interface.4,5
Several physical and chemical mechanisms have been proposed to explain the electron conduction in the memory cell, such as those based on metallic diffusion (electrochemical metallization), valence change, thermo-chemical, and interfacial coupling.6–8 A valence change memristor is controlled by an electric field that induces the formation and rupture of oxygen vacancy filaments to switch the device On (state 1) and Off (state 0), respectively, also called memristive behavior.9 The formation of the filament is initiated by the creation of oxygen vacancies by ionizing the oxygen from the lattice of the oxide switching layer, and these vacancies grow from the cathode to anode while the oxygen ions drift to and are oxidized at the anode/switching layer interface; the electrons, then, can easily flow through this filament, enabling the device in a low resistance state (LRS, state 1).10 Conversely, the filament can be ruptured by re-ionizing the oxygen at the anode/switching layer interface to recombine with the vacancies, creating a conduction gap between the electrode and remnant of the filament and, hence, switching the device to a high resistance state (HRS, state 0).10
Furthermore, the formation and rupture of the filaments can be used by an electric stimulus having short pulses and small amplitude to exhibit multiple states (states beyond 1 and 0); consequently, the device can perform an analogous gradual rise and fall of conductance.11 The gradual rise and fall of the conductance are called potentiation and depression, respectively, mimicking the mammalian brain's analogous synaptic weight response.12 However, the fabrication of analog memristors requires careful design and optimization, which makes the manufacturing process greatly challenging; this is because memristor devices often show digital behavior instead of analog, where the conductance change occurs abruptly.13
Various designs have been proposed to achieve a reliable synaptic response but mostly focus on programming the pulse scheme11 and engineering the switching materials such as bi-layering,14 doping,15 embedding with nanocrystals,16 and surface modification.17 These methods could indeed improve the synaptic response; however, the fundamental question of the relationship between the electron conduction and the structure of the filaments determining such analog and digital behavior in memristor devices is still less examined. In this work, we investigate the conduction channel configuration at the interface responsible for dictating the analog and digital response of the memristors. We explain the occurrence of digital-to-analog transformation in the device, and the conduction mechanism is also proposed by studying the phenomenon observed in devices having different thicknesses.
The device architecture and measurement setup are depicted in Figs. 1(a) and 1(b), respectively. A 15 nm TiN bottom electrode (BE) was deposited onto a Pt/Ti-coated Si-wafer substrate employing the atomic layer deposition technique. TiO2 switching layer films with thicknesses of 16 and 25 nm were deposited onto the bottom electrode. Hereafter, TiN/Ti bilayer top electrodes (TEs) having a diameter of 250 µm were patterned onto the TiO2 films using a metal shadow mask. The sheet resistance of the TiN electrodes is found to be less than 19 Ω/sq. The thicknesses of TiN and Ti are 50 and 15 nm, respectively. The TiO2, TiN, and Ti films were deposited using a DC sputtering system from a Ti target in a mixture of Ar/O2, Ar/N2, and Ar ambience, respectively. The devices made with 16 and 25 nm thick TiO2 films were denoted as D16 and D25, respectively. The electrical characteristics were investigated using an Agilent B1500A semiconductor analyzer. A voltage bias was applied to the top electrode while the bottom electrode was grounded; a current compliance (CC) was used during the positive bias voltage sweep to avoid permanent breakdown. For DC sweep, a negative bias of −1.4 V was used for all devices to switch the device Off. In the case of synaptic measurement, AC pulse schemes were used to induce the response by applying pulse amplitudes of −1.2 and 1 V for depression and potentiation, respectively, with a pulse width of 20 µs. Meanwhile, the pulse read was conducted using an amplitude of 0.1 V with a width of 1 ms. An epoch consists of 500 pulses of depression (D) and 500 pulses of potentiation (P). Note that the synaptic response test was conducted after several switching cycles. The element profile and defect were measured by x-ray photoelectron spectroscopy (XPS, PHI Quantera SXM).

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Accepted/In Press date: 31 October 2021
Published date: 6 December 2021

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Local EPrints ID: 452710
URI: http://eprints.soton.ac.uk/id/eprint/452710
ISSN: 2166-532X
PURE UUID: 447a1dd5-beb1-41e9-a5bc-89c29cce2ad6

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Date deposited: 15 Dec 2021 17:33
Last modified: 17 Jan 2022 17:35

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Contributors

Author: Firman Simanjuntak
Author: Chun-Ling Hsu
Author: Thomas Abbey
Author: Chun-Ling Hsu

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