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Modelling, simulation and verification of 4-phase adiabatic logic design: a VHDL-based approach

Modelling, simulation and verification of 4-phase adiabatic logic design: a VHDL-based approach
Modelling, simulation and verification of 4-phase adiabatic logic design: a VHDL-based approach
The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioural VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach.
0167-9260
144-154
Maheshwari, Sachin
f09ac1de-0e3d-410d-a7e2-f4d54a1459b9
Bartlett, Viv
dd51f33f-e4c7-4e46-8deb-1b3bb699c6de
Kale, Izzet
c95f4beb-432b-4fed-b464-18a4c2e641cf
Maheshwari, Sachin
f09ac1de-0e3d-410d-a7e2-f4d54a1459b9
Bartlett, Viv
dd51f33f-e4c7-4e46-8deb-1b3bb699c6de
Kale, Izzet
c95f4beb-432b-4fed-b464-18a4c2e641cf

Maheshwari, Sachin, Bartlett, Viv and Kale, Izzet (2019) Modelling, simulation and verification of 4-phase adiabatic logic design: a VHDL-based approach. Integration the VLSI Journal, 67, 144-154. (doi:10.1016/j.vlsi.2019.01.007).

Record type: Article

Abstract

The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioural VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach.

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Accepted/In Press date: 22 January 2019
Published date: 28 January 2019

Identifiers

Local EPrints ID: 453368
URI: http://eprints.soton.ac.uk/id/eprint/453368
ISSN: 0167-9260
PURE UUID: a0130ec3-e3e1-417a-b02b-1a797bc257ac

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Date deposited: 13 Jan 2022 18:16
Last modified: 14 Jan 2022 05:01

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Contributors

Author: Sachin Maheshwari
Author: Viv Bartlett
Author: Izzet Kale

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