Experimental demonstration of RRAM-based computational cells for reconfigurable mixed-signal neuro-inspired circuits and systems

Abstract

Modern electronics drive a shift from distributed, cloud and/or mainframe computing towards the ‘edge’. To realise this vision, we need access to hardware technologies that are both energy and scale efficient. During the last decade, the introduction of Resistive Random Access Memory (RRAM), also known as memristors, has fuelled interest in extending conventional circuits’ capabilities. Specifically, their capacity to act as scalable, non-volatile, finely tuneable, electrically programmable resistive elements render them promising candidates for future computer architectures. RRAM technologies have been considered by many as a promising candidate for implementing reconfigurable neuro-inspired circuits and systems capable of processing data in both digital and analogue formats. Presently, there is no extensive study of the behaviour of such circuits when realised physically with real RRAM devices. Hence, there are ample opportunities for developing novel electronic circuits for reconfigurable mixed-signal data processors in silico.
This thesis explores the design, implementation and testing of in-silico data processors capable of mapping data from one information domain to another and enabling a mixed-signal data processing. Through this research, I am introducing RRAM-based circuit designs operationally validated through simulations with state-of-art RRAM device model and then practically implemented proof-of-concept designs of these hybrid RRAM-CMOS circuits on hardware. The hardware implementation and testing of low-complexity primitive RRAM-based circuits that can process information in the analogue domain due to the introduction of programmable RRAM devices is the main contributions through this project. In this work, findings are presented regarding the implementation and testing in hardware of a RRAM-based primitive Multiply-Accumulate circuit, RRAM-enhanced Threshold Logic Gate design and as well as larger circuits on these primitive circuits that are easily integrated into RRAM-based In-Memory Computing (IMC) architectures. A primitive RRAM-based MAC circuit is designed and its behaviour exhibited in both simulation (Cadence Virtuoso Spectre) and in hardware. This circuit is used for a proof-of-concept Winner-Take-All systems that showcases 300fJ energy and 1.4ns delay per operation. Additionally, A RRAM-based Threshold Logic Gate is designed and showcased achieving 27.2µW and 0.14ns per operation. Finally, a RRAM-based Wake-Up Circuit is showcased to be feasible using the the aforementioned circuits inside an IMC system.

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Identifiers

ORCID for Georgios Papandroulidakis: orcid.org/0000-0002-9203-2557

ORCID for Themis Prodromakis: orcid.org/0000-0002-6267-6909

ORCID for Geoffrey Merrett: orcid.org/0000-0003-4980-3894

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