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Real-time hardware architecture for characterising functional brain connectivity from mobile electroencephalogram

Real-time hardware architecture for characterising functional brain connectivity from mobile electroencephalogram
Real-time hardware architecture for characterising functional brain connectivity from mobile electroencephalogram
The usage of transcranial current stimulation has recently gained attention due to its potential as an alternative treatment to mental and neurological disorders, but its usage remains questionable due to the lack of protocols in its implementation. Different studies suggest that functional brain connectivity (FC) can be used to guide the stimulus and provide more accurate treatment. This, combined with wearable electroencephalogram (EEG) systems, opens the possibility for a new treatment where the patient is continuously monitored and the stimulus is correctly applied when needed. However, this approach would require real-time EEG signal processing to characterise the FC, which have only been done in computer software, thus limiting the scope of this treatment. To address this, a new real-time hardware architecture for characterising FC from mobile EEG is proposed in this work. This architecture performs the characterisation in real-time and can be implemented on a field-programmable gate array (FPGA) as a wearable device instead of a computer. To achieve this performance, every process involved in the calculation was analysed and optimised using different design approaches to select the most efficient implementation to decrease the computational complexity, allowing real-time processing and low energy consumption. The architecture was synthesised in an FPGA as a proof-of-concept, and it was able to calculate the FC and its characterisation in a total time of 273.10 µs with a power consumption of 51.84 mW, meeting the timing and energy requirements established for this project. Furthermore, a seizure classifier was created to evaluate the impact in performance using the proposed hardware architecture against its software equivalent. The result showed a maximum difference of 0.15% in the classifier performance, demonstrating that the proposed architecture can be used for the real-time calculation and characterisation of the FC with minimal impact in the final performance.
University of Southampton
Gutierrez Nuno, Rafael, Angel
0d732031-1fc9-40bf-b91f-3af547ea9b54
Gutierrez Nuno, Rafael, Angel
0d732031-1fc9-40bf-b91f-3af547ea9b54
Maharatna, Koushik
93bef0a2-e011-4622-8c56-5447da4cd5dd

Gutierrez Nuno, Rafael, Angel (2021) Real-time hardware architecture for characterising functional brain connectivity from mobile electroencephalogram. University of Southampton, Doctoral Thesis, 143pp.

Record type: Thesis (Doctoral)

Abstract

The usage of transcranial current stimulation has recently gained attention due to its potential as an alternative treatment to mental and neurological disorders, but its usage remains questionable due to the lack of protocols in its implementation. Different studies suggest that functional brain connectivity (FC) can be used to guide the stimulus and provide more accurate treatment. This, combined with wearable electroencephalogram (EEG) systems, opens the possibility for a new treatment where the patient is continuously monitored and the stimulus is correctly applied when needed. However, this approach would require real-time EEG signal processing to characterise the FC, which have only been done in computer software, thus limiting the scope of this treatment. To address this, a new real-time hardware architecture for characterising FC from mobile EEG is proposed in this work. This architecture performs the characterisation in real-time and can be implemented on a field-programmable gate array (FPGA) as a wearable device instead of a computer. To achieve this performance, every process involved in the calculation was analysed and optimised using different design approaches to select the most efficient implementation to decrease the computational complexity, allowing real-time processing and low energy consumption. The architecture was synthesised in an FPGA as a proof-of-concept, and it was able to calculate the FC and its characterisation in a total time of 273.10 µs with a power consumption of 51.84 mW, meeting the timing and energy requirements established for this project. Furthermore, a seizure classifier was created to evaluate the impact in performance using the proposed hardware architecture against its software equivalent. The result showed a maximum difference of 0.15% in the classifier performance, demonstrating that the proposed architecture can be used for the real-time calculation and characterisation of the FC with minimal impact in the final performance.

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More information

Submitted date: November 2021

Identifiers

Local EPrints ID: 456932
URI: http://eprints.soton.ac.uk/id/eprint/456932
PURE UUID: 7de09b32-becd-4c26-8e41-05f06cd09d32
ORCID for Rafael, Angel Gutierrez Nuno: ORCID iD orcid.org/0000-0002-8226-4725

Catalogue record

Date deposited: 17 May 2022 16:52
Last modified: 16 Mar 2024 17:35

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Contributors

Author: Rafael, Angel Gutierrez Nuno ORCID iD
Thesis advisor: Koushik Maharatna

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