Testing techniques and Fault Simulation for analogue CMOS integrated circuitsTitle

Abstract

As size and complexity of Integrated Circuits (ICs) keep increasing, testing those ICs is becoming more challenging task for test engineers. Time-to-Market (TtM) is perhaps the most important parameter in an IC's life cycle. Therefore, one needs to come up with test techniques that give shortest possible TtM, yet cost effective and efficient in terms of acceptable yields. Traditional functional testing is both time consuming and expensive. Alternative technique, structural testing, is well established for digital circuits. For analogue circuits, it seems that it will take a while for structural test to become mature. This is mainly due to the fact that there is still not a standard fault definition for analogue circuits. This thesis deals with problems related to testing analogue circuits. Supply current monitoring is a widely used test technique for digital circuits. Recent research has focused on the application of the technique to analogue circuits. One way to implement the supply current monitoring is to use Built-in Current Sensors (BICSs), which enables Design for Test (DfT) and Built-in Self-Test (BIST). In this thesis a novel BICS is designed for analogue circuits. The BICS was fabricated in O.Spm AMS CYE CMOS (2.5-5.5V, p-sub, 2-metal, 2-poly). Measurement results done on the fabricated IC confirm the correct functionality of the proposed BICS design. Marginal voltage screening is another widely used technique for digital circuits. Variable power supply can be used as a technique for the marginal voltage screening. There is some research on the application of the technique to analogue circuits. In this thesis variable supply voltage technique in conjunction with supply current monitoring technique for analogue circuits is further investigated. It has been shown that up to 82% fault coverage for a complex analogue circuit, a PLL (Phase-Locked Loop), can be achieved using this technique. Fast fault simulation is crucial in terms of test generation for both analogue and digital circuits. In this thesis, new methods of speeding-up analogue fault simulation has been proposed. Simulation results carried out on a number of benchmark circuits have shown that employing these techniques along with the analogue concurrent fault simulation can result in up to 100% fault coverage and up to 4.7 times speed-up in terms of the CPU time. Another way to speed-up the analogue fault simulation is to model an analogue circuit under faulty conditions at a behavioural level. Behavioural fault modelling using analogue HDLs, such as MAST and VHDL-AMS (the IEEE 1076.1 standard) is discussed in this thesis, where it has been shown that using behavioural models developed in this thesis over 373 times speed-up (in terms of the CPU time) is possible compared with the transistor level simulations.

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