Modelling and characterisation of silicon-on-insulator lateral double diffused mosfets for analogue circuit simulation
Modelling and characterisation of silicon-on-insulator lateral double diffused mosfets for analogue circuit simulation
In this thesis a circuit simulator model is developed, based on a detailed study of device physics of the LDMOS. First, the subcircuit modelling approach was followed, resulting in a 'quick-fix' LDMOS model. The drawbacks of this modelling approach are the complexity of the circuit, and convergence problems.
To overcome these disadvantages a compact model is presented. The model has only one internal node, situated in the channel at the transition point from thin gate oxide into field oxide. Both currents are carefully derived, to keep the model as physical as possible. The current under the thin gate oxide is described in terms of the surface potentials, whilst taking into account the lateral doping gradient and the overlap of the gate over the N-drift region. The impact of the thickness of the depletion layer at the buried oxide on the current under the field oxide is studied rigorously, leading to good prediction of the unique high-side behaviour. Next, the complete SOI LDMOS charge model is set out, presenting a promising new approach to deal with the unusual charge partitioning in the LDMOS.
DC simulations with the compact model match the measured characteristics well for a wide range of geometries, with self-heating and high-side effects being accounted for. The simulated and measured capacitance characteristics for a range of geometries show excellent qualitative behaviour, and demonstrate the soundness of the new charge model.
The model has been implemented in the SPICE circuit simulator and careful formulation and coding has led to a very robust SOI LDMOS model, which converges easily without the need for node setting. The model is evaluated thoroughly, using a set of simulations based on the SEMATECH tests. Finally, two special analogue circuits were designed and fabricated to allow circuit level evaluation of the accuracy and robustness of our model. The model predicts the measurement results well for circuits containing LV and MV transistors, and also gives a reasonable prediction of the HV circuits. We can conclude that, with further optimisation, our compact SOI LDMOS model can provide a practical and reliable simulation tool for commercial design use.
University of Southampton
D'Halleweyn, Nele
ecd17d10-a506-4a7f-8240-16d2f3b2f360
2002
D'Halleweyn, Nele
ecd17d10-a506-4a7f-8240-16d2f3b2f360
D'Halleweyn, Nele
(2002)
Modelling and characterisation of silicon-on-insulator lateral double diffused mosfets for analogue circuit simulation.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
In this thesis a circuit simulator model is developed, based on a detailed study of device physics of the LDMOS. First, the subcircuit modelling approach was followed, resulting in a 'quick-fix' LDMOS model. The drawbacks of this modelling approach are the complexity of the circuit, and convergence problems.
To overcome these disadvantages a compact model is presented. The model has only one internal node, situated in the channel at the transition point from thin gate oxide into field oxide. Both currents are carefully derived, to keep the model as physical as possible. The current under the thin gate oxide is described in terms of the surface potentials, whilst taking into account the lateral doping gradient and the overlap of the gate over the N-drift region. The impact of the thickness of the depletion layer at the buried oxide on the current under the field oxide is studied rigorously, leading to good prediction of the unique high-side behaviour. Next, the complete SOI LDMOS charge model is set out, presenting a promising new approach to deal with the unusual charge partitioning in the LDMOS.
DC simulations with the compact model match the measured characteristics well for a wide range of geometries, with self-heating and high-side effects being accounted for. The simulated and measured capacitance characteristics for a range of geometries show excellent qualitative behaviour, and demonstrate the soundness of the new charge model.
The model has been implemented in the SPICE circuit simulator and careful formulation and coding has led to a very robust SOI LDMOS model, which converges easily without the need for node setting. The model is evaluated thoroughly, using a set of simulations based on the SEMATECH tests. Finally, two special analogue circuits were designed and fabricated to allow circuit level evaluation of the accuracy and robustness of our model. The model predicts the measurement results well for circuits containing LV and MV transistors, and also gives a reasonable prediction of the HV circuits. We can conclude that, with further optimisation, our compact SOI LDMOS model can provide a practical and reliable simulation tool for commercial design use.
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Published date: 2002
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Local EPrints ID: 464647
URI: http://eprints.soton.ac.uk/id/eprint/464647
PURE UUID: 081223e8-7a3a-4770-8374-140bb79d55c0
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Date deposited: 04 Jul 2022 23:53
Last modified: 16 Mar 2024 19:40
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Author:
Nele D'Halleweyn
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