Switched-current filters and phase-locked loops : methods and tools

Abstract

The switched-current (SI) technique has started  a new era in analogue sampled-data signal processing where the benefit of requiring no linear floating capacitors and the suitability for low-voltage operation facilitates mixed-signal design on a standard digital CMOS process.  This thesis considers the analysis, design automation and realisation of two fundamental analogue blocks, filters and phase-locked loops (PLLs), using SI technology.

A systematic design flow, from specification to layout, for SI filters employing the wave synthesis technique is presented.  A key feature of the flow is a novel power-aware scaling procedure which simultaneously reduces the filter power consumption and total harmonic distortion.  A computer aided design (CAD) methodology called AutoSIF has been developed to automate the filter design flow and facilitate rapid generation of SI wave filter circuits.  PLLs are employed in numerous applications ranging from clock recovery to demodulation and frequency synthesis.  Despite the possible advantages of applying the SI technique to PLLS, there has been very little research in this area.  This thesis describes the methodical design of SL PLLs and proposes a novel 2^nd over architecture that does not require a separate phase detector, leading to a more compact implementation than conventional approaches.  Theoretical analysis and transistor level design procedures are presented for the proposed PLL architecture and a further CAD methodology, AutoPLL, has been developed to automate and support the associated design flow.

Simulation results based on foundry BSim3v3 models are provided for the designed SI filters and PLLs.  To analyse the practical performance of the power-aware filter design flow, a prototype chip has been fabricated and measured results show close agreement with theoretical analysis and simulation.  Two PLL case studies are presented including a 10MHz frequency shift keying (FSK) demodulator and 500 MHz frequency synthesiser which demonstrate that the proposed SI PLL architecture is capable of producing low power designs of comparable performance to the commercial state of the art.

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