Fabrication of lateral silicon germanium heterojunction bipolar transistors

Abstract

The fabrication of lateral SiGe heterojunction bipolar transistors requires the development of new processing stages, device design and modelling. In this work, techniques for cavity fabrication, surface preparation and con & ned selective epitaxial growth are developed and a new design of lateral SiGe heterojunction transistor is proposed. Two types of cavity were fabricated in this work, the open-sided cavity and the SOI cavity. The open-sided cavity allows confined growth to be carried out A-om a planar seed window, while the SOI cavity allows growth from a vertical (sidewall) seed. To ensure warp-6ee and rigid structures, the wall of the cavities has to be made 6om an LTO/nitride/LTO sandwich. For sacriScial etching, the use of dry (SFg) and wet etch (KOH) processes were found to be suitable for the removal of polysihcon/silicon sacrificial layer, however, the use of wet processing meant a higher probability of stiction. It is also shown that the fabrication of SOI cavities should include a silicon sidewall ripphng reduction step (using KOH), to create an epi-ready vertical seed. Silane-only selective epitaxy is found to give good quality epitaxial layers, however the growth thickness that can be achieved before selectivity is lost is limited by an incubation period of -30 minutes. In addition, the high growth temperature (980°C) is found to cause oxide pitting and etching at silicon/oxide sidewall areas. Furthermore, development for a selective silicon germanium process at low temperatures has so far led to non-selective growth. A new DCS/SiH4/H2 epitaxy process has been established that provides good quality selective epitaxial layers at between 750°C - 930°C. At 850°C, uniformity was found to be +/- 5%, with a vertical and lateral growth rate (G-om a planar seed) of 38 nm/min and 11 nm/min, respectively. Confined and unconfined lateral growth 6om a vertical seed of up to 0.5 ^im and 1 ^m, respectively, has been demonstrated. The epitaxy process, which has an activation energy of 2.4eV, was found to be largely unaffected by any local loading effects. In addition, silicon germanium epitaxial layers have also been successfully grown. As with the silane-only process, DCS/SiH4/H2 growth, selectivity is found to be lost after an incubation period, which at 850°C is close to 90 minutes. Based on the cavity and epitaxy processes that have been developed, a lateral SiCre heterojunction bipolar transistor has been proposed. From simulations, the design shows promise, with/r a n d f i g u r es of 2.0 and 8.0 GHz, respectively. With further development in the DCS/SiH^/Hz epitaxy process to allow zw j'zA/ doping, the design may achieve an/rand figure of 6.3 and 15.8 GHz, respectively. Further scaling and design optimisation is likely to yield high performance devices.

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