Architectural synthesis of analogue filters from behavioural VHDL-AMS descriptions
Architectural synthesis of analogue filters from behavioural VHDL-AMS descriptions
The primary aim of this research is to investigate and develop techniques for VHDL-AMS-based synthesis of analogue filters suitable for use in mixed-signal ASICs where behavioural models are especially important. Particular emphasis is put on architectural optimisation with the aim to identify the most suitable circuit topologies.
The novel contributions can be briefly summarised as follows. New methods have been presented to extract synthesisable VHDL-AMS constructs from behavioural filter models using parse trees. They can be extended to support a more general, mixed-signal synthesis system based on VHDL-AMS. An effective architectural optimisation engine for analogue filter synthesis has been developed to minimise transfer function accuracy errors and power consumption. The engine is based on three-tier architectural and parametric optimisation, in which a combination of heuristic and systematic search algorithms provides a possibility of global optimisation. The parametric optimiser relies on full HSPICE simulation to ensure accurate circuit performance evaluation.
The new methods are implemented in a demonstrator system named FIST (Filter Synthesis Tool), and were successfully applied to several case studies of 1 GHz integrated analogue filter circuits designed for implementation in a 0.35μm CMOS technology.
The method of using parse trees to extract circuit-level structures from high-level descriptions proved to be effective. It was shown that parse trees allow for easy detection of synthesisable constructs and support recursive static evaluations of expressions necessary in calculation of filter parameters. This technique provides a groundwork from which more general VHDL-AMS-based synthesis systems can be developed.
University of Southampton
Azlee Hamid, Fazrena
513e2255-3678-4485-96cb-2b9119bd508e
2004
Azlee Hamid, Fazrena
513e2255-3678-4485-96cb-2b9119bd508e
Azlee Hamid, Fazrena
(2004)
Architectural synthesis of analogue filters from behavioural VHDL-AMS descriptions.
University of Southampton, Doctoral Thesis.
Record type:
Thesis
(Doctoral)
Abstract
The primary aim of this research is to investigate and develop techniques for VHDL-AMS-based synthesis of analogue filters suitable for use in mixed-signal ASICs where behavioural models are especially important. Particular emphasis is put on architectural optimisation with the aim to identify the most suitable circuit topologies.
The novel contributions can be briefly summarised as follows. New methods have been presented to extract synthesisable VHDL-AMS constructs from behavioural filter models using parse trees. They can be extended to support a more general, mixed-signal synthesis system based on VHDL-AMS. An effective architectural optimisation engine for analogue filter synthesis has been developed to minimise transfer function accuracy errors and power consumption. The engine is based on three-tier architectural and parametric optimisation, in which a combination of heuristic and systematic search algorithms provides a possibility of global optimisation. The parametric optimiser relies on full HSPICE simulation to ensure accurate circuit performance evaluation.
The new methods are implemented in a demonstrator system named FIST (Filter Synthesis Tool), and were successfully applied to several case studies of 1 GHz integrated analogue filter circuits designed for implementation in a 0.35μm CMOS technology.
The method of using parse trees to extract circuit-level structures from high-level descriptions proved to be effective. It was shown that parse trees allow for easy detection of synthesisable constructs and support recursive static evaluations of expressions necessary in calculation of filter parameters. This technique provides a groundwork from which more general VHDL-AMS-based synthesis systems can be developed.
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Published date: 2004
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Local EPrints ID: 465792
URI: http://eprints.soton.ac.uk/id/eprint/465792
PURE UUID: d4bb4a03-d4c9-4a8d-a728-e6c163fa14f9
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Date deposited: 05 Jul 2022 03:06
Last modified: 16 Mar 2024 20:22
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Author:
Fazrena Azlee Hamid
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