Fabrication of vertical MOSFETs with reduced parasitics and incorporating a dielectric pocket

Abstract

Single, double and surround gate FILOX vertical nMOSFETs with reduced gate overlap capacitance have been fabricated.  In these devices, a 40 nm thick FILOX oxide covers the horizontal silicon area, while the vertical sidewalls of the active pillar only contain the 3.3 nm thick gate oxide.  Single and double gate transistors have been successfully fabricated and characterized.  The threshold voltage roll-off of surround gate vertical MOSFETs with channel length ranging between 90 nm and 140 nm has been investigated, showing that the FILOX process must be carefully tuned in order to minimize the short channel effects.  The transfer characteristics of long channel FILOX vertical MOSFETs in drain on top and drain on bottom measurement configurations are found to be symmetric in on-state operation.  On the other hand, the off-state drain leakage currents of the devices are found to be asymmetric when the source and the drain are interchanged, with gate induced drain leakage (GIDL) being higher in the drain on bottom configuration and body leakage being higher in the drain on top configuration.

Surround gate vertical nMOSFETs with shallow drain junctions and dielectric pockets have been fabricated using a novel approach.  This process is fully compatible with conventional planar CMOS technology, does not require epitaxial growth and allows sub-100 nm vertical MOSFETs with shallow drain junctions to be fabricated without requiring advanced photolithography.  Dielectric pocket vertical nMOSFETs with channel length down to 70 nm have been produced and display good electrical characteristics.  The drain of the devices is connected to the channel by a polysilicon spacer with a minimum thickness of about 20 nm.

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