High Level Synthesis with interconnect prediction

Abstract

A HLS system is presented called MOODS (Multiple Objective Optimisation in Data and control path Synthesis), which has been developed by Southampton University and LME Design Automation Ltd.  In order to improve the level of estimation of the behaviour of design at the physical level, i.e. after the design has been implemented in hardware, interconnect predictors will be introduced into MOODS. Circuit partitioning will form the foundations of all interconnect predictors by forming a relative placement.  This relative placement can then be used to estimate the average interconnect length of a circuit and quickly obtain a floorplan.  This thesis shows that the average interconnect delay of a design on FPGA correlates to a high degree with average interconnect length predicted by MOODS, and when used to guide optimisation design optimality improves significantly. It is also shown that when an APR tool is given hierarchical information obtained during circuit partitioning to guide placement and routing of FPGA, the overall design optimality in terms of area and delay is improved.  The floorplan can then be used to find individual Wire Lengths, as the approximate position of every module on the chip will now be known.  These individual Wire Lengths will then be shown to be highly desirable when deciding on whether to perform certain transformations to the design architecture, during optimization.  Finally, the future development of interconnect predictors with their applications will be shown.

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