An investigation of high level synthesis for computational hardware

Abstract

This thesis is concerned with the development and validation of a specific application high level synthesis methods to implement computational algorithms in digital hardware.  Special emphasis is placed upon datapath structure and accuracy analysis and optimisation between computational error and hardware implementation costs.

The first part of the thesis concentrates on the high level synthesis of computational algorithms.  We investigate how the arithmetic characteristics of the hardware affects implementation costs.  In the following, the problem of choosing different arithmetic characteristics for each functional unit considering circuit cost is addressed.  We use a symbolic method of computational error analysis in which the computational errors are characterised as sets of statistical symbols.

The proposed accuracy modelling is applied to a new architecture for datapath synthesis.  Hierarchical target architecture is proposed which is built on a multiple-width multiple-way partitioned bus which provides the capability of parallel implementation of computational algorithms as well as flexibility in synthesis and optimisation. This architecture is based on an extension to the shared bus structure which is built by connecting a set of series and parallel bus segments building up a communication medium for all functional units.  In combination with the multiple word-length design approach, each bus segment, and all the connected functional units to it, are allocated to a distinct bit-width.

Results demonstrate that by customising the structure and building blocks of computational intensive datapaths, savings can be made in the overall area, delay, and power consumption of a hardware implementation.  This approach represents an improvement when compared with the previous work in this field and provides more understanding of implementing the computational algorithms into the customised hardware.

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