The development of CCD parallel transfer structures for analogue signal processing

Abstract

The application of CCDs to the detection of marine radar targets buried in sea clutter using signal integration techniques is discussed. The improvement in target detectability using integrators that employ a conventional (serial) CCD is severely restricted by the build-up of residual signals caused by charge, transfer inefficiency: A new CCD architecture is described that substantially overcomes this limitation since signal charge transfers, and consequently residuals, are kept to a minimum. In this novel structure, a floating-gate tapped CCD operating as a digital shift register is used to address sequentially analogue gates which store each radar return in a series of CCD storage areas. The floating-gate sensing scheme is analysed using a new technique based upon charge balance which was developed to investigate these structures rigorously. The analysis shows that large address pulses can be generated which can be used to drive each analogue gate directly without intermediate MOST amplification. Although analogue delay devices employing storage techniques similar to those described in this thesis have been described previously, they have used ROST addressing and gating. On the other hand, the exclusive use of CCD structures enables the high speed performance of these devices to be exploited. Two integration schemes are investigated: non-recursive integration in which returns are summed with equal weighting, and recursive integration in which returns are summed with exponential weighting. Since the recursive scheme requires a smaller and less complex chip, more attention has been paid to this implementation. The design and fabrication of a test chip to investigate the performance of the address CCD and storage areas is described. Close correlation between the theoretical and measured response of the floating-gate taps of the address register was observed. Unfortunately, a mask error prevented satisfactory operation of the storage areas. The design and fabrication of a second recursive test device incorporating a number of modifications is also described, and some experimental data which demonstrate the ability of the device to store a digital signal are presented. The thesis concludes with a theoretical investigation as to the most appropriate method of implementing the non-recursive integrator. It is suggested that a multiple floating-gate charge sensing schemeis used to perform the integration; since this technique is inherently non-linear, an experimental investigation of this method has also been carried out. The results of an analysis using the charge balance method agree well with the measured response.

More information

Identifiers

Catalogue record

Export record

ASCII CitationAtomBibTeXData Cite XMLDublin CoreDublin CoreEP3 XMLEndNoteHTML CitationHTML CitationHTML ListJSONMETSMODSMPEG-21 DIDLOpenURL ContextObjectOpenURL ContextObject in SpanRDF+N-TriplesRDF+N3RDF+XMLRIOXX2 XMLReferReference ManagerSimple Metadata