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Blockwise parallel frozen bit generation for polar codes

Blockwise parallel frozen bit generation for polar codes
Blockwise parallel frozen bit generation for polar codes
An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=┌n/w┐) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w┐) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=┌n/w┐ clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.
US20200204197A1
Maunder, Rob
76099323-7d58-4732-a98f-22a662ccba6c
Brejza, Matthew Felix
a761342e-e140-45a7-ad48-095a6628af17
Zhong, Shida
68341271-2339-4e05-b7fc-ec6cbb22c1b3
Perez Andrade, Isaac
51aa4dad-b027-4b31-8cf7-1225889be1dc
Chen, Taihai
c5107a09-2235-4adf-b71b-c1e4a3534732

Maunder, Rob, Brejza, Matthew Felix, Zhong, Shida, Perez Andrade, Isaac and Chen, Taihai (Inventors) (2021) Blockwise parallel frozen bit generation for polar codes. US20200204197A1.

Record type: Patent

Abstract

An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=┌n/w┐) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w┐) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=┌n/w┐ clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.

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US20200204197A1 - Version of Record
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Published date: 22 June 2021

Identifiers

Local EPrints ID: 473956
URI: http://eprints.soton.ac.uk/id/eprint/473956
PURE UUID: 09e2f305-beee-4918-8df2-ddaa33cabafa
ORCID for Rob Maunder: ORCID iD orcid.org/0000-0002-7944-2615

Catalogue record

Date deposited: 06 Feb 2023 17:43
Last modified: 17 Mar 2024 03:14

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Contributors

Inventor: Rob Maunder ORCID iD
Inventor: Matthew Felix Brejza
Inventor: Shida Zhong
Inventor: Isaac Perez Andrade
Inventor: Taihai Chen

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