Off and on again: Modeling and optimizing intermittent computing systems

Abstract

Intermittent computing (IC) is a vital technology for realizing IoT at a vast scale. By harvesting energy from the environment, and leveraging non-volatile memory (NVM) to retain computational progress through power cycles, IC enables untethered and battery-free devices that perform incremental computation whenever ambient energy is available. The backbone of IC is NVM, and recent advances in energy-efficient byte addressable NVM have the potential to expand the application domain of IC substantially. The tight interaction between energy and execution does, however, cause complexities that require specialized modeling, hardware design, and software design; complexities that hamper adoption. This thesis is focused on optimizing IC using software and hardware support leveraging energy-efficient NVM, and also on system-level modeling of IC systems to enable such research. Supporting IC on commercially available microcontrollers is important to lower the barrier to entry, and for adoption of IC in real-world applications. However, current methods suffer from inefficient state retention. To address this issue, this thesis proposes Managed State, a new page-based memory manager that tracks used and modified regions of memory to reduce the overhead of state retention by 26–87 %. To make IC as efficient, robust and useful as possible, however, software support alone is insufficient. Hardware support for IC is needed; and to research system-level hardware support for IC, electronic system-level modeling is the most reasonable approach. However, modeling IC presents unique challenges that current modeling tools do not support, most prominent of which is the tight interactions between energy and execution. To model IC systems, this thesis proposes a new full-system simulator, named Fused, that specifically models the interplay between energy and execution in IC devices. Using Fused, this thesis then explores new hardware support for IC that leverages energy-efficient and byte-addressable NVMs. The result is MEMIC, a memory architecture with hardware support that improves performance by 13–39 % compared to the state-of-art, and furthermore allows systems to operate under harsher conditions. MEMIC strives to combine volatile- and non-volatile memory in such a way that the operations of IC are as efficient as possible, while also maximizing computational performance per joule.

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Identifiers

ORCID for Sivert T. Sliper: orcid.org/0000-0002-8991-3783

ORCID for Geoffrey Merrett: orcid.org/0000-0003-4980-3894

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