A 100-Gb/s PAM4 optical transmitter in a 3-D-integrated SiPh-CMOS platform using segmented MOSCAP modulators

Abstract

This article presents a 100-Gb/s four-level pulse-amplitude modulation (PAM4) optical transmitter system implemented in a 3-D-integrated silicon photonics-CMOS platform. The photonics chip includes a push–pull segmented Mach–Zehnder modulator (MZM) structure using highly capacitive (415 fF–1.1 pF), yet optically efficient ( VπL=0.8V⋅ cm) metal–oxide–silicon capacitor (MOSCAP) phase modulators. Two pairs of U-shaped modulator segments with effective lengths of 170 and 450 μm are driven at 50 GBd by a dual-channel 28-nm CMOS driver, which is flip-chip bonded to the photonics chip. The driver cores utilize digitally controllable pre-distortion (PD) and inductive peaking to achieve sufficient electro-optical bandwidth (EOBW). The drivers deliver 1.2-Vppd swing to modulators using a 0.9-V supply and on-chip serializers that generate 50-Gb/s data streams. The electronics chip consumes 240 mW achieving 2.4-pJ/bit energy efficiency. The overall EOBW, without any PD, is increased by approximately 56% and 48% for the 170- and 450- μm segments, respectively, when compared to their EOBW measured by 65-GHz 50- Ω terminated probes. The optical input power to the photonics chip is +10 dBm, and an erbium-doped fiber amplifier amplifies output signals by 11 dB. The 50-Gb/s nonreturn to zero (NRZ) optical raw eye diagram exhibits 4.3-dB extinction ratio (ER) and 1.2 dBm of optical modulation amplitude (OMA). The 100-Gb/s PAM4 optical raw eye diagram shows 4.3-dB ER and 1.4-dBm OMA with a transmitter dispersion eye closure quaternary (TDECQ) of 1.53 dB after a five-tap feed-forward-equalization (FFE) filter. The PAM4 TDECQ changes by 53% when the temperature is increased from 30 °C to 90 °C at the optimum forward bias voltage of 1 V.

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