On the feasibility of using current-based monitors to detect ageing in CMOS Circuits

Abstract

The ageing effects have taken the attention as it shows the unavoidable sign as the device size is shrinking. Three most crucial ageing effects that are known to give threat to circuits reliability and performances are Bias-Temperature-Instability (BTI), Hot Carrier Injection (HCI) and Time-Dependent Dielectric Breakdown (TDDB). And between these ageing effects, BTI is the most prominent ageing effect than others. These effects have been reported to compromise CMOS technology in sub-100nm region that degrades the critical performance parameter, which includes the shifting of threshold voltage and degradation of the drain current. These degradations are then led to the degradation of circuit frequency, affecting the overall efficiency of the whole circuit. This phenomenon eventually shortens the lifespan of the chip to only a few years. In this report, we discuss some of the effects of BTI (particularly NBTI since it is more dominant than PBTI), focussing on the degradation of the drain current. The significance of drain current for becoming a dominant device ageing barometer is revealed. An NBTI ageing sensor is proposed based on monitoring the drain current with optimised implementation on critical gates. Based on the results simulated, the incorporation of drain current degradation as being the ageing sensor monitored parameter has significantly higher resolution in term of degradation compared to the threshold voltage degradation for the same period of stress time. This report is also discussed on the feasibility of employing such monitoring circuit that measured drain current for ageing effects prediction mechanism.

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Identifiers

ORCID for Mark Zwolinski: orcid.org/0000-0002-2230-625X

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