Advancing logic locking: a new strategy combining dynamic and zero-knowledge techniques

Abstract

The IC industry's growth has heightened attention to hardware security, particularly in the last decade. Major IC companies, aiming to cut costs, have begun outsourcing parts of their supply chain instead of managing it entirely in-house. This cost-saving strategy increases vulnerability to malicious attacks. To counter this, various defence mechanisms like logic locking have been proposed, offering protection against unauthorized IP access and supply chain threats with minimal design flow alterations.
Despite logic locking's many advantages in hardware defence, it confronts two major challenges. Firstly, significant efforts in the field have aimed at extracting secret keys from encrypted designs, particularly to clone IP. The SAT attack notably undermines the efficacy of logic locking. To mitigate this, various techniques like point function-based logic locking (PFB) have emerged, balancing SAT attack resilience with minimal product overhead. However, PFB's fixed mechanism inherently exposes specific properties, making it vulnerable to targeted attacks. Secondly, traditional logic locking presumes the design house's trustworthiness. However, internal malicious actors are a real threat in practice, against which current logic locking methods are ineffective.
This thesis introduces Dynamic Logic Locking (DLL), a new logic locking strategy to address the aforementioned security concerns. DLL's dynamic mechanism, unlike traditional methods, uses randomly generated locking blocks to counter SAT and other logic locking attacks. Its unique mechanism for each design eliminates structural vulnerabilities, unlike conventional fixed-mechanism blocks. Moreover, DLL's random block generation allows for zero-knowledge implementation by designers, who need not know the block's structure or secret key details. This makes DLL robust even against internal malicious attacks within the design house.
This thesis also introduces DLL-se, a sequential variant of DLL, expanding its application to sequential circuits for increased utility. Additionally, it presents a Python-based logic locking tool capable of integrating various logic locking types, including DLL, into Verilog netlists and simulating attacks on logic locking. With its clear GUI, the tool is accessible to designers and students and is suitable for hardware design and educational research.

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Identifiers

ORCID for Yue Zhang: orcid.org/0009-0002-9275-1989

ORCID for Basel Halak: orcid.org/0000-0003-3470-7226

ORCID for Leonardo Aniello: orcid.org/0000-0003-2886-8445

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