Low-temperature Al2O3/ZnO thin-film transistors for 3D heterogeneous integration: interface engineering, bias stress instability, and reliability mechanisms

Zeng, Jiale (2026) Low-temperature Al2O3/ZnO thin-film transistors for 3D heterogeneous integration: interface engineering, bias stress instability, and reliability mechanisms. University of Southampton, Doctoral Thesis, 197pp.

Record type: Thesis (Doctoral)

Abstract

Back-end-of-line (BEOL) process scaling and the emergence of three-dimensional heterogeneous integration (3D-HI) demand thin-film transistors (TFTs) that can be integrated within a limited thermal budget while maintaining high electrical performance (µ_FE > 10 cm² V⁻¹ s ⁻¹ ), long-term reliability (|∆V_TH| < 0.5 V after 1 h stress), and low manufacturing cost. Zinc oxide (ZnO) has attracted sustained interest as a channel material owing to its wide bandgap (∼3.3 eV), optical transparency, and compatibility with low-temperature processing. However, the stability of ZnO TFTs remains a major bottleneck, particularly in devices employing atomic-layer-deposited (ALD) aluminium oxide (Al₂O₃) gate dielectrics, where the dielectric/semiconductor interface critically governs bias-stress degradation. This thesis systematically investigates the interdependence between Al₂O₃ deposition temperature (150–300 ^◦C), interface-trap density (D_it), and bias-stress instability mechanisms in ZnO TFTs. A unified device platform was developed, incorporating both global p-Si bottom gates and patterned AZO bottom gates, enabling separation of intrinsic dielectric effects from gate-geometry-induced field crowding. Cross-sectional transmission electron microscopy (TEM), together with SILVACO/TCAD simulations, confirms the presence of localised electric-field enhancement at wet-etched sharp gate corners, which promotes percolation-type leakage paths and soft breakdown, particularly under high drain bias (V_D = 15 V), where threshold-voltage shifts exceeding 1.2 V are observed. A clear trade-off between mobility and reliability is identified as a function of Al₂O₃ deposition temperature. Devices fabricated with Al₂O₃ deposited at 150^◦C exhibit lower field-effect mobility (µ_FE ≈ 4.8 cm² V⁻¹ s⁻¹ ) yet the most stable behaviour, with small hysteresis (< 0.2 V) and reduced trap density (N_trap ∼ 3 × 10¹² cm⁻² ), consistent with hydrogen-assisted defect passivation. By contrast, films deposited at 300 ^◦C are denser and yield higher mobility (µ_FE ≈ 8.7 cm² V⁻¹ s ⁻¹ ), but suffer from substantially increased hysteresis (> 1.0 V) and higher trap density (N_trap > 1 × 10¹³ cm⁻² ). Capacitance–voltage (C–V) analysis shows a dielectric constant of k ≈ 8.2 and a stable oxide capacitance (C_ox ≈ 7.5 × 10⁻⁷ F cm⁻² ). Under positive bias stress (PBS, +10 V) in the dark, significant charge trapping is observed with ∆V_TH up to +2.3 V, whereas negative bias stress (NBS) in the dark is comparatively weak (∆V_TH > −0.2 V), consistent with limited de-trapping dynamics in p-Si gated structures. Optical excitation at 365 nm (photon energy ∼3.4 eV) profoundly alters the stress response through photo-generated carriers. Under illumination, PBS exhibits an initial rapid ∆V_TH shift (e.g., ∼ +0.8 V within 60 s), followed by partial saturation consistent with enhanced de-trapping. Conversely, NBS becomes strongly destabilising, producing large negative shifts (e.g., −1.5 V after 1 h) accompanied by marked subthreshold-slope degradation. These results demonstrate that illumination accelerates both trapping and de-trapping processes and highlights the dynamic charge balance at the Al₂O₃/ZnO interface. By synthesising structural, chemical, and electrical analyses, this thesis establishes a comprehensive reliability map for Al₂O₃/ZnO TFTs under BEOL-compatible conditions. Three practical design strategies are proposed: (i) gate-geometry engineering to mitigate field crowding and suppress edge-initiated percolation leakage, (ii) interface/dielectric optimisation using lower deposition temperatures (typically ≲ 200 ^◦C) to leverage hydrogen-assisted passivation, and (iii) control of plasma chemistry during PEALD to reduce sub-oxide defects. Collectively, these principles provide a pathway to stabilise oxide TFTs for 3D-HI platforms, flexible electronics, and low-power integrated systems.