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A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs

A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs
A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have become more competitive compared to bulk, due to their lower parasitic capacitances and leakage currents. The shift towards high frequency, low power circuitry, coupled with the increased maturity of SOI process technologies, have made SOI a genuinely costeffective solution for leading edge applications.
The original STAG2 model, developed at the University of Southampton, UK, was among the first compact circuit simulation models to specifically model the behaviour of Partially-Depleted (PD) SOI devices. STAG2 was a robust, surface-potential based compact model, employing closed-form equations to minimise simulation times for large circuits. It was able to simulate circuits in DC, small signal, and transient modes, and particular care was taken to ensure that convergence problems were kept to a minimum.
In this thesis, the ongoing development of the STAG model, culminating in the release of a new version, STAG3, is described. STAG3 is intended to make the STAG model applicable to process technologies down to 100nm. To this end, a number of major model improvements were undertaken, including: a new core surface potential model, new vertical and lateral field mobility models, quantum mechanical models, the ability to model non-uniform vertical doping profiles, and other miscellaneous effects relevant to deep submicron devices such as polysilicon depletion, velocity overshoot, and the reverse short channel effect.
As with the previous versions of STAG, emphasis has been placed on ensuring that model equations are numerically robust, as well as closed-form wherever possible, in order to minimise convergence problems and circuit simulation times. The STAG3 model has been evaluated with devices manufactured in PD-SOI technologies down to 0.25?m, and was found to give good matching to experimental data across a range of device sizes and biases, whilst requiring only a single set of model parameters.
Benson, James
4fbc1fae-fc2d-4752-95b3-ff7376a6219c
Benson, James
4fbc1fae-fc2d-4752-95b3-ff7376a6219c
Redman-White, William
d5376167-c925-460f-8e9c-13bffda8e0bf

Benson, James (2009) A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs. University of Southampton, School of Electronics and Computer Science, Doctoral Thesis, 168pp.

Record type: Thesis (Doctoral)

Abstract

With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have become more competitive compared to bulk, due to their lower parasitic capacitances and leakage currents. The shift towards high frequency, low power circuitry, coupled with the increased maturity of SOI process technologies, have made SOI a genuinely costeffective solution for leading edge applications.
The original STAG2 model, developed at the University of Southampton, UK, was among the first compact circuit simulation models to specifically model the behaviour of Partially-Depleted (PD) SOI devices. STAG2 was a robust, surface-potential based compact model, employing closed-form equations to minimise simulation times for large circuits. It was able to simulate circuits in DC, small signal, and transient modes, and particular care was taken to ensure that convergence problems were kept to a minimum.
In this thesis, the ongoing development of the STAG model, culminating in the release of a new version, STAG3, is described. STAG3 is intended to make the STAG model applicable to process technologies down to 100nm. To this end, a number of major model improvements were undertaken, including: a new core surface potential model, new vertical and lateral field mobility models, quantum mechanical models, the ability to model non-uniform vertical doping profiles, and other miscellaneous effects relevant to deep submicron devices such as polysilicon depletion, velocity overshoot, and the reverse short channel effect.
As with the previous versions of STAG, emphasis has been placed on ensuring that model equations are numerically robust, as well as closed-form wherever possible, in order to minimise convergence problems and circuit simulation times. The STAG3 model has been evaluated with devices manufactured in PD-SOI technologies down to 0.25?m, and was found to give good matching to experimental data across a range of device sizes and biases, whilst requiring only a single set of model parameters.

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Published date: April 2009
Organisations: University of Southampton

Identifiers

Local EPrints ID: 69885
URI: https://eprints.soton.ac.uk/id/eprint/69885
PURE UUID: 958dccba-cbba-4973-98f9-f62fccdce0b5

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Date deposited: 08 Dec 2009
Last modified: 19 Jul 2017 00:05

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