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Design of a robust digital current controller for a grid connected interleaved inverter

Design of a robust digital current controller for a grid connected interleaved inverter
Design of a robust digital current controller for a grid connected interleaved inverter
This paper is concerned with the design and practical implementation of a robust digital current controller for a threephase voltage source grid-connected interleaved inverter. Each phase consists of 6 half-bridge channels connected in parallel.
Due to the current ripple cancellation of the interleaving topology, only small output filter capacitors are required which provide high impedance to grid voltage harmonics and hence better current quality compared to traditional 2-level LCL topology.
The current in each inductor is controlled via a single feedback loop. A feedforward loop of the grid voltage is incorporated to compensate for the grid disturbance. To control the high resonance frequency of the filter, high sampling and switching frequencies are required. Alternatively, resistors in series with the filter capacitors are used to provide damping.
This method becomes practically possible due to the low magnitude of the current of the capacitors and consequently low power dissipation in the damping resistors. The paper also studies in detail the effects of computational time delay and grid impedance variation on system stability. A phase lag compensator incorporated in the inductor current loop is designed to increase system immunity to grid impedance variations. Simulation and practical results are presented to validate the design.
Abu-sara, M. A.
cde8e173-f938-4210-8b9d-d1bf3a9a429a
Sharkh, S. M.
c8445516-dafe-41c2-b7e8-c21e295e56b9
Abu-sara, M. A.
cde8e173-f938-4210-8b9d-d1bf3a9a429a
Sharkh, S. M.
c8445516-dafe-41c2-b7e8-c21e295e56b9

Abu-sara, M. A. and Sharkh, S. M. (2010) Design of a robust digital current controller for a grid connected interleaved inverter. ISIE 2010 IEEE International Symposium on Industrial Electronics. 04 - 07 Jul 2010. 6 pp .

Record type: Conference or Workshop Item (Paper)

Abstract

This paper is concerned with the design and practical implementation of a robust digital current controller for a threephase voltage source grid-connected interleaved inverter. Each phase consists of 6 half-bridge channels connected in parallel.
Due to the current ripple cancellation of the interleaving topology, only small output filter capacitors are required which provide high impedance to grid voltage harmonics and hence better current quality compared to traditional 2-level LCL topology.
The current in each inductor is controlled via a single feedback loop. A feedforward loop of the grid voltage is incorporated to compensate for the grid disturbance. To control the high resonance frequency of the filter, high sampling and switching frequencies are required. Alternatively, resistors in series with the filter capacitors are used to provide damping.
This method becomes practically possible due to the low magnitude of the current of the capacitors and consequently low power dissipation in the damping resistors. The paper also studies in detail the effects of computational time delay and grid impedance variation on system stability. A phase lag compensator incorporated in the inductor current loop is designed to increase system immunity to grid impedance variations. Simulation and practical results are presented to validate the design.

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Accepted/In Press date: 18 March 2010
Venue - Dates: ISIE 2010 IEEE International Symposium on Industrial Electronics, 2010-07-04 - 2010-07-07
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Local EPrints ID: 73643
URI: https://eprints.soton.ac.uk/id/eprint/73643
PURE UUID: 64fb116f-f759-4461-8153-258fac9bc83b

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Date deposited: 18 Mar 2010
Last modified: 18 Jul 2017 23:49

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