Stress analysis and optimization of a Flip chip on flex electronic packaging method for functional electronic textiles

Abstract

A method for packaging integrated circuit (IC) silicon die in thin flexible circuits has been investigated that enables circuits to be subsequently integrated within textile yarns. This paper presents an investigation into the required materials and component dimensions in order to maximize the reliability of the packaging method. Two die sizes of 3.5 mm x 8 mm x 0.53 mm and 2 mm x 2mm x 0.1 mm have been simulated and evaluated experimentally under shear load and during bending. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. Three under-fill adhesives (EP30AO, EP37-3FLF and Epo-Tek 301 2fl), three highly flexible adhesive (Loctite 4860, Loctite 480 and Loctite 4902) and three substrates (Kapton, Mylar and PEEK) have been evaluated and the optimal thickness of each is found. The Kapton substrate, together with the EP37-3FLF adhesive, were identified as the best materials combination, with the optimum under-fill and substrate thickness identified as 0.05 mm.

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